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[23.128.96.38]) by mx.google.com with ESMTPS id o16-20020a056a0015d000b0068e44a5e7ffsi9818589pfu.90.2023.10.10.02.12.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 02:12:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 15E528329AA2; Tue, 10 Oct 2023 02:12:39 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229787AbjJJJMa (ORCPT + 99 others); Tue, 10 Oct 2023 05:12:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229516AbjJJJM3 (ORCPT ); Tue, 10 Oct 2023 05:12:29 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DA3AC9F; Tue, 10 Oct 2023 02:12:26 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5E6C9C15; Tue, 10 Oct 2023 02:13:07 -0700 (PDT) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 714683F762; Tue, 10 Oct 2023 02:12:25 -0700 (PDT) Date: Tue, 10 Oct 2023 10:12:23 +0100 From: Sudeep Holla To: "Peng Fan (OSS)" Cc: cristian.marussi@arm.com, linux-arm-kernel@lists.infradead.org, Sudeep Holla , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, ranjani.vaidyanathan@nxp.com, glen.wienecke@nxp.com, Peng Fan Subject: Re: [RFC] firmware: arm_scmi: clock: add fixed clock attribute support Message-ID: <20231010091223.rvcyrgbjcrmjzmvp@bogus> References: <20231010022911.4106863-1-peng.fan@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231010022911.4106863-1-peng.fan@oss.nxp.com> X-Spam-Status: No, score=2.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 10 Oct 2023 02:12:39 -0700 (PDT) X-Spam-Level: ** On Tue, Oct 10, 2023 at 10:29:11AM +0800, Peng Fan (OSS) wrote: > From: Peng Fan > > There are clocks: > system critical, not allow linux to disable, change rate > allow linux to get rate, because some periphals will use the frequency > to configure periphals. > > So introduce an attribute to indicated FIXED clock > > Signed-off-by: Peng Fan > --- > drivers/clk/clk-scmi.c | 6 ++++++ > drivers/firmware/arm_scmi/clock.c | 5 ++++- > include/linux/scmi_protocol.h | 1 + > 3 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c > index 8cbe24789c24..a539a35bd45a 100644 > --- a/drivers/clk/clk-scmi.c > +++ b/drivers/clk/clk-scmi.c > @@ -182,6 +182,10 @@ static const struct clk_ops scmi_clk_ops = { > .determine_rate = scmi_clk_determine_rate, > }; > > +static const struct clk_ops scmi_fixed_rate_clk_ops = { > + .recalc_rate = scmi_clk_recalc_rate, > +}; > + > static const struct clk_ops scmi_atomic_clk_ops = { > .recalc_rate = scmi_clk_recalc_rate, > .round_rate = scmi_clk_round_rate, > @@ -293,6 +297,8 @@ static int scmi_clocks_probe(struct scmi_device *sdev) > if (is_atomic && > sclk->info->enable_latency <= atomic_threshold) > scmi_ops = &scmi_atomic_clk_ops; > + else if (sclk->info->rate_fixed) > + scmi_ops = &scmi_fixed_rate_clk_ops; > else > scmi_ops = &scmi_clk_ops; > > diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c > index ddaef34cd88b..8c52db539e54 100644 > --- a/drivers/firmware/arm_scmi/clock.c > +++ b/drivers/firmware/arm_scmi/clock.c > @@ -46,6 +46,7 @@ struct scmi_msg_resp_clock_attributes { > #define SUPPORTS_RATE_CHANGE_REQUESTED_NOTIF(x) ((x) & BIT(30)) > #define SUPPORTS_EXTENDED_NAMES(x) ((x) & BIT(29)) > #define SUPPORTS_PARENT_CLOCK(x) ((x) & BIT(28)) > +#define SUPPORTS_FIXED_RATE_CLOCK(x) ((x) & BIT(27)) I don't see this in the specification, am I missing something ? And why do we need it. Can't this be discrete clock with only one clock rate ? Or step clock with both lowest and highest the same and step being 0. At-least I don't see the need to change the spec for this and hence no need to assign any attribute bit-field to represent the same. -- Regards, Sudeep