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From:   Claudiu <claudiu.beznea@tuxon.dev>
To:     geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        mturquette@baylibre.com, sboyd@kernel.org
Cc:     linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
        Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH 0/6] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S
Date:   Tue, 10 Oct 2023 16:26:55 +0300
Message-Id: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com>
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From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Hi,

This series enables Renesas RZ/G3S (R9A08G045) SDHI1 and SDHI2 clocks and
resets and adds proper DT entries. SDHI1 is connected to a uSD interface
available on Smarc-II carrier board while SDHI2 is connected to a
uSD interface available on RZ/G3S Smarc Module (SoM).

Along with SDHI1 and SDHI2 support I've added 2 small cleanup patches
(patch 1/6 and 6/6).

Please not that series is based on patches at [1].

Thank you,
Claudiu Beznea

[1] https://lore.kernel.org/all/20231006103959.197485-1-claudiu.beznea.uj@bp.renesas.com/

Claudiu Beznea (6):
  clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
  clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and
    SDHI2
  arm64: dts: renesas: r9a08g045: Add nodes for SDHI1 and SDHI2
  arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2
  arm64: dts: renesas: rzg3s-smarc: Enable SDHI1
  arm64: dts: renesas: rzg3s: Fix dtbs_check

 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    | 31 +++++++++
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     | 62 ++++++++++++++++-
 arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi  | 66 +++++++++++++++++++
 drivers/clk/renesas/r9a08g045-cpg.c           | 34 ++++++++++
 drivers/clk/renesas/rzg2l-cpg.c               |  2 +-
 5 files changed, 193 insertions(+), 2 deletions(-)

-- 
2.39.2