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[209.85.208.50]) by smtp.gmail.com with ESMTPSA id o20-20020a170906289400b009930042510csm8658686ejd.222.2023.10.10.10.32.38 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Oct 2023 10:32:39 -0700 (PDT) Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-53636f98538so10285048a12.1 for ; Tue, 10 Oct 2023 10:32:38 -0700 (PDT) X-Received: by 2002:aa7:df86:0:b0:52a:1d9c:83ff with SMTP id b6-20020aa7df86000000b0052a1d9c83ffmr17044118edy.1.1696959158578; Tue, 10 Oct 2023 10:32:38 -0700 (PDT) MIME-Version: 1.0 References: <20231010164234.140750-1-ubizjak@gmail.com> In-Reply-To: <20231010164234.140750-1-ubizjak@gmail.com> From: Linus Torvalds Date: Tue, 10 Oct 2023 10:32:21 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 -tip] x86/percpu: Use C for arch_raw_cpu_ptr() To: Uros Bizjak Cc: x86@kernel.org, linux-kernel@vger.kernel.org, Nadav Amit , Andy Lutomirski , Brian Gerst , Denys Vlasenko , "H . Peter Anvin" , Peter Zijlstra , Thomas Gleixner , Josh Poimboeuf Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 10 Oct 2023 10:32:55 -0700 (PDT) On Tue, 10 Oct 2023 at 09:43, Uros Bizjak wrote: > > Implementing arch_raw_cpu_ptr() in C, allows the compiler to perform > better optimizations, such as setting an appropriate base to compute > the address instead of an add instruction. Hmm. I wonder.. > + tcp_ptr__ = __raw_cpu_read(, this_cpu_off) + (unsigned long)(ptr); \ Do we really even want to use __raw_cpu_read(this_cpu_off) at all? On my machines (I tested an Intel 8th gen laptop, and my AMD Zen 2 Threadripper machine), 'rdgsbase' seems to be basically two cycles. I wonder if we'd be better off using that, rather than doing the load. Yes, a load that hits in L1D$ will schedule better, so it's "cheaper" in that sense. The rdgsbase instruction *probably* will end up only decoding in the first decoder etc. But we're talking single-cycle kind of effects, and the rdgsbase case should be much better from a cache perspective and might use fewer memory pipeline resources to offset the fact that it uses an unusual front end decoder resource... Yes, yes, we'd have to make it an alternative, and do something like static __always_inline unsigned long new_cpu_offset(void) { unsigned long res; asm(ALTERNATIVE( "movq %%gs:this_cpu_off,%0", "rdgsbase %0", X86_FEATURE_FSGSBASE) : "=r" (res)); return res; } but it still seems fairly straightforward. Hmm? Linus