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Date:   Wed, 11 Oct 2023 12:45:55 +0700
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Subject: Re: [PATCH v11 1/1] vfio/nvgpu: Add vfio pci variant module for grace
 hopper
To:     Alex Williamson <alex.williamson@redhat.com>
Cc:     ankita@nvidia.com, jgg@nvidia.com, yishaih@nvidia.com,
        shameerali.kolothum.thodi@huawei.com, kevin.tian@intel.com,
        aniketa@nvidia.com, cjia@nvidia.com, kwankhede@nvidia.com,
        targupta@nvidia.com, vsethi@nvidia.com, acurrid@nvidia.com,
        apopple@nvidia.com, jhubbard@nvidia.com, danw@nvidia.com,
        anuaggarwal@nvidia.com, dnigam@nvidia.com, udhoke@nvidia.com,
        kvm@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20231007202254.30385-1-ankita@nvidia.com>
 <ZSHykZ2GgSn0fE_x@debian.me>
 <20231009133612.3fdd86a9.alex.williamson@redhat.com>
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From:   Bagas Sanjaya <bagasdotme@gmail.com>
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On 10/10/2023 02:36, Alex Williamson wrote:
> On Sun, 8 Oct 2023 07:06:41 +0700
> Bagas Sanjaya <bagasdotme@gmail.com> wrote:
> 
>> On Sun, Oct 08, 2023 at 01:52:54AM +0530, ankita@nvidia.com wrote:
>>> PCI BAR are aligned to the power-of-2, but the actual memory on the
>>> device may not. A read or write access to the physical address from the
>>> last device PFN up to the next power-of-2 aligned physical address
>>> results in reading ~0 and dropped writes.
>>>   
>>
>> Reading garbage or padding in that case?
>>
>> Confused...
> 
> The coherent memory size is rounded to a power-of-2 to be compliant with
> PCI BAR semantics, but reading beyond the implemented size fills the
> return buffer with -1 data, as is common on many platforms when reading
> from an unimplemented section of the address space.  Thanks,
> 
> Alex
> 

Thanks for the explanation!

-- 
An old man doll... just what I always wanted! - Clara