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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697003531; x=1697608331; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uB2f3GYH/kpgRnRbL88LHcmeeqsYhInJn57hhNzYiD0=; b=DtbjCPVYjRC/xPhYlZWl2LP7FWIfsEp5ZqnvMFOkcnd4zzFAo8K7IZOhesf8JUFRiQ eFHJ39MTX1HFAsOfzC73wTRu32/S4HvUoAOHDyJKXIgks68X85Et0fAxi0pZd/7y1WCT krns8c8gOaRm+wznCoVP2wjkK+Pa/t+8dDDkEiKqeu5TQlI+1BbndNeT/yHmxlsZFSal hmdohbFXPTgMhYzxONZ58xYG3/q0VcOHGlAH4cC/8jYgVe0HrNFz+6quHAwBKG8yxj+T IX3iYki7SZNnidvNN0Y8u0eZpa1nQb5KtXZQWv8n1NrM1kOmbFWpx+M56ME4gtg9qFF4 vSZw== X-Gm-Message-State: AOJu0YxF6ebknS6WVcQ7Rlw5WHzY94h33L/1pKRlkSh1qbfPrcqcMa15 +C6Pie7RrMkKx16/GhK+OX976j6ArjhKd6zTnGqrN+CyMiRNG2Yx X-Received: by 2002:a05:6a20:914b:b0:158:7fdf:66df with SMTP id x11-20020a056a20914b00b001587fdf66dfmr25459333pzc.18.1697003530678; Tue, 10 Oct 2023 22:52:10 -0700 (PDT) MIME-Version: 1.0 References: <20231010170503.657189-1-apatel@ventanamicro.com> <20231010170503.657189-5-apatel@ventanamicro.com> <2023101053-scholar-resolute-a9a0@gregkh> In-Reply-To: <2023101053-scholar-resolute-a9a0@gregkh> From: Anup Patel Date: Wed, 11 Oct 2023 11:22:00 +0530 Message-ID: Subject: Re: [PATCH 4/6] tty/serial: Add RISC-V SBI debug console based earlycon To: Greg Kroah-Hartman Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Jiri Slaby , Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 10 Oct 2023 22:52:20 -0700 (PDT) On Tue, Oct 10, 2023 at 10:46=E2=80=AFPM Greg Kroah-Hartman wrote: > > On Tue, Oct 10, 2023 at 10:35:01PM +0530, Anup Patel wrote: > > We extend the existing RISC-V SBI earlycon support to use the new > > RISC-V SBI debug console extension. > > > > Signed-off-by: Anup Patel > > --- > > drivers/tty/serial/Kconfig | 2 +- > > drivers/tty/serial/earlycon-riscv-sbi.c | 35 ++++++++++++++++++++++--- > > 2 files changed, 32 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig > > index bdc568a4ab66..cec46091a716 100644 > > --- a/drivers/tty/serial/Kconfig > > +++ b/drivers/tty/serial/Kconfig > > @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST > > > > config SERIAL_EARLYCON_RISCV_SBI > > bool "Early console using RISC-V SBI" > > - depends on RISCV_SBI_V01 > > + depends on RISCV_SBI > > select SERIAL_CORE > > select SERIAL_CORE_CONSOLE > > select SERIAL_EARLYCON > > diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/seri= al/earlycon-riscv-sbi.c > > index 27afb0b74ea7..b1da34e8d8cd 100644 > > --- a/drivers/tty/serial/earlycon-riscv-sbi.c > > +++ b/drivers/tty/serial/earlycon-riscv-sbi.c > > @@ -10,22 +10,49 @@ > > #include > > #include > > > > +#ifdef CONFIG_RISCV_SBI_V01 > > static void sbi_putc(struct uart_port *port, unsigned char c) > > { > > sbi_console_putchar(c); > > } > > > > -static void sbi_console_write(struct console *con, > > - const char *s, unsigned n) > > +static void sbi_0_1_console_write(struct console *con, > > + const char *s, unsigned int n) > > { > > struct earlycon_device *dev =3D con->data; > > uart_console_write(&dev->port, s, n, sbi_putc); > > } > > +#endif > > + > > +static void sbi_dbcn_console_write(struct console *con, > > + const char *s, unsigned int n) > > +{ > > + phys_addr_t pa =3D __pa(s); > > + > > + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, > > +#ifdef CONFIG_32BIT > > + n, pa, (u64)pa >> 32, > > +#else > > + n, pa, 0, > > +#endif > > Again, no #ifdef in .c files please. Okay, I will remove #ifdef from here as well. > > thanks, > > greg k-h Thanks, Anup