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From:   Jacky Huang <ychuang570808@gmail.com>
To:     linus.walleij@linaro.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        p.zabel@pengutronix.de, j.neuschaefer@gmx.net
Cc:     linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        schung@nuvoton.com, Jacky Huang <ychuang3@nuvoton.com>
Subject: [PATCH 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control
Date:   Wed, 11 Oct 2023 09:05:08 +0000
Message-Id: <20231011090510.114476-3-ychuang570808@gmail.com>
In-Reply-To: <20231011090510.114476-1-ychuang570808@gmail.com>
References: <20231011090510.114476-1-ychuang570808@gmail.com>
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From: Jacky Huang <ychuang3@nuvoton.com>

Add the dt-bindings header for nuvoton ma35d1 pinctrl, that gets shared
between the pin control driver and pin configuration in the dts.

Add documentation to describe nuvoton ma35d1 pin control and GPIO.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
 .../pinctrl/nuvoton,ma35d1-pinctrl.yaml       | 180 ++++++++++++++++++
 include/dt-bindings/pinctrl/ma35d1-pinfunc.h  |  38 ++++
 2 files changed, 218 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
 create mode 100644 include/dt-bindings/pinctrl/ma35d1-pinfunc.h

diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
new file mode 100644
index 000000000000..0ddedbad4b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 pin control and GPIO
+
+maintainers:
+  - Shan-Chun Hung <schung@nuvoton.com>
+
+properties:
+  compatible:
+    enum:
+      - nuvoton,ma35d1-pinctrl
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  nuvoton,sys:
+    description:
+      phandle to the syscon node
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      maxItems: 1
+
+  ranges: true
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+patternProperties:
+  "gpio[a-n]@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+    properties:
+
+      gpio-controller: true
+
+      '#gpio-cells':
+        const: 2
+
+      reg:
+        maxItems: 1
+
+      clocks:
+        maxItems: 1
+
+      interrupt-controller: true
+
+      '#interrupt-cells':
+        const: 2
+
+      interrupts:
+        description:
+          The interrupt outputs to sysirq.
+        maxItems: 1
+
+    required:
+      - reg
+      - interrupts
+      - interrupt-controller
+      - '#interrupt-cells'
+      - gpio-controller
+      - '#gpio-cells'
+
+  "pcfg-[a-z0-9-.]+$":
+    type: object
+    description:
+      A pinctrl node should contain at least one subnodes representing the
+      pinctrl groups available on the machine. Each subnode will list the
+      pins it needs, and how they should be configured, with regard to muxer
+      configuration, pullups, drive strength, input enable/disable and input
+      schmitt.
+
+    allOf:
+      - $ref: pincfg-node.yaml#
+
+    properties:
+      bias-disable: true
+
+      bias-pull-down: true
+
+      bias-pull-up: true
+
+      drive-strength:
+        minimum: 0
+        maximum: 7
+
+      input-enable: true
+
+      input-schmitt-enable: true
+
+      power-source:
+        description:
+          I/O voltage in millivolt.
+        enum: [ 1800, 3300 ]
+
+additionalProperties:
+  type: object
+  additionalProperties:
+    type: object
+    properties:
+      nuvoton,pin:
+        description:
+          Each entry consists of 4 parameters and represents the mux and config
+          setting for one pin.
+        $ref: /schemas/types.yaml#/definitions/uint32-matrix
+        minItems: 1
+        items:
+          items:
+            - minimum: 0x80
+              maximum: 0xec
+              description:
+                The pinctrl register offset in syscon registers.
+            - minimum: 0
+              maximum: 30
+              description:
+                The bit offset in the pinctrl register.
+            - minimum: 0
+              maximum: 15
+              description:
+                The multi-function pin value.
+            - description:
+                The phandle of a node contains the generic pinconfig options
+                to use as described in pinctrl-bindings.txt.
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+    #include <dt-bindings/pinctrl/ma35d1-pinfunc.h>
+
+    pinctrl@40040000 {
+        compatible = "nuvoton,ma35d1-pinctrl";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        nuvoton,sys = <&sys>;
+        ranges = <0 0x40040000 0xc00>;
+
+        gpioa@40040000 {
+                reg = <0x0 0x40>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk GPA_GATE>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        pcfg_default: pcfg-default {
+                slew-rate = <0>;
+                input-schmitt-disable;
+                bias-disable;
+                power-source = <3300>;
+                drive-strength = <0>;
+        };
+    };
+
+    pinctrl {
+        uart13 {
+                pinctrl_uart13: uart13grp {
+                        nuvoton,pins =
+                                <MA35_SYS_REG_GPH_H 24 2 &pcfg_default>,
+                                <MA35_SYS_REG_GPH_H 28 2 &pcfg_default>;
+                };
+        };
+    };
+
+    serial@407d0000 {
+        compatible = "nuvoton,ma35d1-uart";
+        reg = <0x407d0000 0x100>;
+        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk UART13_GATE>;
+        pinctrl-0 = <&pinctrl_uart13>;
+    };
diff --git a/include/dt-bindings/pinctrl/ma35d1-pinfunc.h b/include/dt-bindings/pinctrl/ma35d1-pinfunc.h
new file mode 100644
index 000000000000..a2609d466dc9
--- /dev/null
+++ b/include/dt-bindings/pinctrl/ma35d1-pinfunc.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Nuvoton Technologies.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H
+#define __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H
+
+#define MA35_SYS_REG_GPA_L	0x80
+#define MA35_SYS_REG_GPA_H	0x84
+#define MA35_SYS_REG_GPB_L	0x88
+#define MA35_SYS_REG_GPB_H	0x8c
+#define MA35_SYS_REG_GPC_L	0x90
+#define MA35_SYS_REG_GPC_H	0x94
+#define MA35_SYS_REG_GPD_L	0x98
+#define MA35_SYS_REG_GPD_H	0x9c
+#define MA35_SYS_REG_GPE_L	0xa0
+#define MA35_SYS_REG_GPE_H	0xa4
+#define MA35_SYS_REG_GPF_L	0xa8
+#define MA35_SYS_REG_GPF_H	0xac
+#define MA35_SYS_REG_GPG_L	0xb0
+#define MA35_SYS_REG_GPG_H	0xb4
+#define MA35_SYS_REG_GPH_L	0xb8
+#define MA35_SYS_REG_GPH_H	0xbc
+#define MA35_SYS_REG_GPI_L	0xc0
+#define MA35_SYS_REG_GPI_H	0xc4
+#define MA35_SYS_REG_GPJ_L	0xc8
+#define MA35_SYS_REG_GPJ_H	0xcc
+#define MA35_SYS_REG_GPK_L	0xd0
+#define MA35_SYS_REG_GPK_H	0xd4
+#define MA35_SYS_REG_GPL_L	0xd8
+#define MA35_SYS_REG_GPL_H	0xdc
+#define MA35_SYS_REG_GPM_L	0xe0
+#define MA35_SYS_REG_GPM_H	0xe4
+#define MA35_SYS_REG_GPN_L	0xe8
+#define MA35_SYS_REG_GPN_H	0xec
+
+#endif /* __DT_BINDINGS_PINCTRL_NUVOTON_MA35D1_H */
-- 
2.34.1