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[23.128.96.38]) by mx.google.com with ESMTPS id bx13-20020a056a00428d00b00666c9148d03si3048419pfb.6.2023.10.11.05.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 05:24:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 6E2088022ADB; Wed, 11 Oct 2023 05:24:28 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346916AbjJKMXt (ORCPT + 99 others); Wed, 11 Oct 2023 08:23:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346724AbjJKMXT (ORCPT ); Wed, 11 Oct 2023 08:23:19 -0400 Received: from outbound-smtp28.blacknight.com (outbound-smtp28.blacknight.com [81.17.249.11]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B7BCEE for ; Wed, 11 Oct 2023 05:20:31 -0700 (PDT) Received: from mail.blacknight.com (pemlinmail04.blacknight.ie [81.17.254.17]) by outbound-smtp28.blacknight.com (Postfix) with ESMTPS id 5F44E4A034 for ; Wed, 11 Oct 2023 13:20:30 +0100 (IST) Received: (qmail 19080 invoked from network); 11 Oct 2023 12:20:30 -0000 Received: from unknown (HELO techsingularity.net) (mgorman@techsingularity.net@[84.203.197.19]) by 81.17.254.9 with ESMTPSA (AES256-SHA encrypted, authenticated); 11 Oct 2023 12:20:30 -0000 Date: Wed, 11 Oct 2023 13:20:27 +0100 From: Mel Gorman To: Huang Ying Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Arjan Van De Ven , Sudeep Holla , Andrew Morton , Vlastimil Babka , David Hildenbrand , Johannes Weiner , Dave Hansen , Michal Hocko , Pavel Tatashin , Matthew Wilcox , Christoph Lameter Subject: Re: [PATCH 02/10] cacheinfo: calculate per-CPU data cache size Message-ID: <20231011122027.pw3uw32sdxxqjsrq@techsingularity.net> References: <20230920061856.257597-1-ying.huang@intel.com> <20230920061856.257597-3-ying.huang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <20230920061856.257597-3-ying.huang@intel.com> X-Spam-Status: No, score=2.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Wed, 11 Oct 2023 05:24:28 -0700 (PDT) X-Spam-Level: ** On Wed, Sep 20, 2023 at 02:18:48PM +0800, Huang Ying wrote: > Per-CPU data cache size is useful information. For example, it can be > used to determine per-CPU cache size. So, in this patch, the data > cache size for each CPU is calculated via data_cache_size / > shared_cpu_weight. > > A brute-force algorithm to iterate all online CPUs is used to avoid > to allocate an extra cpumask, especially in offline callback. > > Signed-off-by: "Huang, Ying" It's not necessarily relevant to the patch, but at least the scheduler also stores some per-cpu topology information such as sd_llc_size -- the number of CPUs sharing the same last-level-cache as this CPU. It may be worth unifying this at some point if it's common that per-cpu information is too fine and per-zone or per-node information is too coarse. This would be particularly true when considering locking granularity, > Cc: Sudeep Holla > Cc: Andrew Morton > Cc: Mel Gorman > Cc: Vlastimil Babka > Cc: David Hildenbrand > Cc: Johannes Weiner > Cc: Dave Hansen > Cc: Michal Hocko > Cc: Pavel Tatashin > Cc: Matthew Wilcox > Cc: Christoph Lameter > --- > drivers/base/cacheinfo.c | 42 ++++++++++++++++++++++++++++++++++++++- > include/linux/cacheinfo.h | 1 + > 2 files changed, 42 insertions(+), 1 deletion(-) > > diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c > index cbae8be1fe52..3e8951a3fbab 100644 > --- a/drivers/base/cacheinfo.c > +++ b/drivers/base/cacheinfo.c > @@ -898,6 +898,41 @@ static int cache_add_dev(unsigned int cpu) > return rc; > } > > +static void update_data_cache_size_cpu(unsigned int cpu) > +{ > + struct cpu_cacheinfo *ci; > + struct cacheinfo *leaf; > + unsigned int i, nr_shared; > + unsigned int size_data = 0; > + > + if (!per_cpu_cacheinfo(cpu)) > + return; > + > + ci = ci_cacheinfo(cpu); > + for (i = 0; i < cache_leaves(cpu); i++) { > + leaf = per_cpu_cacheinfo_idx(cpu, i); > + if (leaf->type != CACHE_TYPE_DATA && > + leaf->type != CACHE_TYPE_UNIFIED) > + continue; > + nr_shared = cpumask_weight(&leaf->shared_cpu_map); > + if (!nr_shared) > + continue; > + size_data += leaf->size / nr_shared; > + } > + ci->size_data = size_data; > +} This needs comments. It would be nice to add a comment on top describing the limitation of CACHE_TYPE_UNIFIED here in the context of update_data_cache_size_cpu(). The L2 cache could be unified but much smaller than a L3 or other last-level-cache. It's not clear from the code what level of cache is being used due to a lack of familiarity of the cpu_cacheinfo code but size_data is not the size of a cache, it appears to be the share of a cache a CPU would have under ideal circumstances. However, as it appears to also be iterating hierarchy then this may not be accurate. Caches may or may not allow data to be duplicated between levels so the value may be inaccurate. A respin of the patch is not necessary but a follow-on patch adding clarifing comments would be very welcome covering o What levels of cache are being used o Describe what size_data actually is and preferably rename the field to be more explicit as "size" could be the total cache capacity, the cache slice under ideal circumstances or even the number of CPUs sharing that cache. The cache details *may* need a follow-on patch if the size_data value is misleading. If it is a hierarchy and the value does not always represent the slice of cache a CPU could have under ideal circumstances then the value should be based on the LLC only so that it is predictable across architectures. -- Mel Gorman SUSE Labs