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Wed, 11 Oct 2023 12:40:59 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39BCewWw022591 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 12:40:58 GMT Received: from [10.253.39.162] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 11 Oct 2023 05:40:54 -0700 Message-ID: Date: Wed, 11 Oct 2023 20:40:52 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v9 4/4] clk: qcom: add clock controller driver for qca8386/qca8084 Content-Language: en-US To: Konrad Dybcio , Bryan O'Donoghue , , , , , , , , , , CC: , , , , References: <20230923112105.18102-1-quic_luoj@quicinc.com> <20230923112105.18102-5-quic_luoj@quicinc.com> <10bcb0cc-19db-4914-bbc4-ef79c238a70d@linaro.org> <49c8a8ff-bdb9-a523-9587-d2a46d401e41@quicinc.com> From: Jie Luo In-Reply-To: Content-Type: text/plain; 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Wed, 11 Oct 2023 05:41:26 -0700 (PDT) On 10/11/2023 7:32 PM, Konrad Dybcio wrote: > > > On 10/11/23 13:26, Jie Luo wrote: >> >> >> On 10/11/2023 6:25 PM, Bryan O'Donoghue wrote: >>> On 23/09/2023 12:21, Luo Jie wrote: >>>> The clock controller driver of qca8386/qca8084 is registered >>>> as the MDIO device, the hardware register is accessed by MDIO bus >>>> that is normally used to access general PHY device, which is >>>> different from the current existed qcom clock controller drivers >>>> using ioremap to access hardware clock registers. >>> >>> "nsscc-qca8k is accessed via an MDIO bus" >>> >>>> MDIO bus is common utilized by both qca8386/qca8084 and other >>> >>> commonly >>> >>>> PHY devices, so the mutex lock mdio_bus->mdio_lock should be >>>> used instead of using the mutex lock of remap. >>>> >>>> To access the hardware clock registers of qca8386/qca8084, there >>>> is special MDIO frame sequence(three MDIO read/write operations) >>>> need to be sent to device. >>> >>> "there is a special MDIO frame sequence" >>> >>> "which needs to be sent to the device" >> >> I will update the comments, thanks Bryan. >> >>> >>> the following indentation splat from checkpatch >>> >>> CHECK: Alignment should match open parenthesis >>> #2071: FILE: drivers/clk/qcom/nsscc-qca8k.c:2004: >>> +        ret = __mdiobus_write(bus, switch_phy_id, (reg | >>> QCA8K_REG_DATA_UPPER_16_BITS), >>> +                upper_16_bits(val)); >>> >>> CHECK: Alignment should match open parenthesis >>> #2131: FILE: drivers/clk/qcom/nsscc-qca8k.c:2064: >>> +static int qca8k_regmap_update_bits(void *context, unsigned int >>> regaddr, >>> +        unsigned int mask, unsigned int value) >>> >>> total: 0 errors, 1 warnings, 2 checks, 2162 lines checked >>> >>> NOTE: For some of the reported defects, checkpatch may be able to >>>        mechanically convert to the typical style using --fix or >>> --fix-inplace. >>> >>> 0004-clk-qcom-add-clock-controller-driver-for-qca8386-qca.patch has >>> style problems, please review. >> >> Thanks Bryan for the review. The code line mentioned by CHECK is more >> than 100 columns, so i separate the lines. > Please read what checkpatch tells you. > > It asks you to change > > very_long_func_name(arg1, arg2, >     arg3); > > to > > very_long_func_name(arg1, arg2, >             arg3); > > (remember tab len is 8 for the linux kernel) > > Konrad Got it, thanks Konrad for the reminder.