Received: by 2002:a05:7412:d8a:b0:e2:908c:2ebd with SMTP id b10csp179523rdg; Thu, 12 Oct 2023 02:25:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH8ljAAIjX/3kOhSWbMjD647z1Pn5veY9IJ/Zlo09tEKid/ez781MJz0JF9PyV4pklw/807 X-Received: by 2002:a17:902:e551:b0:1c9:e2ed:6702 with SMTP id n17-20020a170902e55100b001c9e2ed6702mr958232plf.27.1697102708510; Thu, 12 Oct 2023 02:25:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697102708; cv=none; d=google.com; s=arc-20160816; b=GwZzYWgV4FlMjG7sWGw1c6mjO+NGvHvsNLMyQqXHXbGzWSRjVTFhkXKs9Un6NN/dAp zVD5uAGcJlSx+E1HfYysUXwWi5hWlXQfp6QG4lYT1Z5byPw18ry3r8q3dL4pyfvp85r1 RLytNMCkGraDSXREhRkwUJ7PmmA149kwn/J+tzy8lBpNIyKyNOvFdnnze9KZha0gkjXW nD8mpPvWirxz6UEImfx7AraW3MsfiiCu1gskq9pDjLfB44d3BhmpKWSMHHw6JABxpCZs IVfEssP5zd3nu+vsreFReRZ5GEqKFG1V15yKO7Ng+BhCvJ3JlxUFc2ecynf5uSF1jtWC 3jCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=9lXHWjePnrR/4JrXpQzVbFVkLl3nGQmNRjEuLQYpsEI=; fh=DY4+6vFcMlUG2Fs2tNneJi+pvVqMEJ7iL0qZZVVVwmo=; b=FzdM19sXWYsck6oOO2bgHgJrW2LR2QZG2PE1DvTMuT8VcIw6pWYiR01XaU0gmO50pQ 4HC5TRZQ9fOwnF1/XWAOjJ13B+/L/WDsW4AWZ0C3eNp6M4Y3bNPyDEC/jzTy852x4MtF DblUXfVUw4NzENvgEf64nNZ9K6BWPdqe9GVpOKVWeicp3L/mwoA1A5kfL+BB1h4rJ2t1 Uc69oGZk/KZI2hshQnh2oQQvv5sWQAtjIeK6TdEFl69k7PwzAOSNvjLx55ojcETc/Qee 4rZ6xVfWYoVg/zQ6sxk57/bekDjh0L8bxKz75heCWobB7kkdgegYWx/YejI3NfyvWZE8 7xXQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id k14-20020a056a00168e00b0069343bdd500si14392939pfc.319.2023.10.12.02.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:25:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id A081581A32B2; Thu, 12 Oct 2023 02:25:03 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235388AbjJLJYx (ORCPT + 99 others); Thu, 12 Oct 2023 05:24:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235399AbjJLJYw (ORCPT ); Thu, 12 Oct 2023 05:24:52 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C7B6F91 for ; Thu, 12 Oct 2023 02:24:50 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E7DB13D5; Thu, 12 Oct 2023 02:25:31 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.81.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6CD6A3F762; Thu, 12 Oct 2023 02:24:49 -0700 (PDT) Date: Thu, 12 Oct 2023 10:24:46 +0100 From: Mark Rutland To: James Clark Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, zhangshaokun@hisilicon.com, Will Deacon , linux-kernel@vger.kernel.org Subject: Re: [PATCH] driver: perf: arm_pmuv3: Read PMMIR_EL1 unconditionally Message-ID: References: <20231009075631.193208-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:25:03 -0700 (PDT) On Mon, Oct 09, 2023 at 09:59:19AM +0100, James Clark wrote: > On 09/10/2023 08:56, Anshuman Khandual wrote: > > PMMIR_EL1 needs to be captured in 'armpmu->reg_pmmir', for all appropriate > > PMU version implementations where the register is available and reading it > > is valid . Hence checking for bus slot event presence is redundant and can > > be dropped. > > > > Cc: Will Deacon > > Cc: Mark Rutland > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > Signed-off-by: Anshuman Khandual > > --- > > This applies on v6.6-rc5. > > > > drivers/perf/arm_pmuv3.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > > index 1e72b486c033..9fc1b6da5106 100644 > > --- a/drivers/perf/arm_pmuv3.c > > +++ b/drivers/perf/arm_pmuv3.c > > @@ -1129,7 +1129,7 @@ static void __armv8pmu_probe_pmu(void *info) > > pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); > > > > /* store PMMIR register for sysfs */ > > - if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31))) > > + if (is_pmuv3p4(pmuver)) > > cpu_pmu->reg_pmmir = read_pmmir(); > > else > > cpu_pmu->reg_pmmir = 0; > > > This does have the side effect of showing non-zero values in caps/slots > even when the STALL_SLOT event isn't implemented. I think that's the > scenario that the original commit (f5be3a61fd) was trying to avoid: > > /sys/bus/event_source/devices/armv8_pmuv3_0/caps/slots is exposed > under sysfs. [If] Both ARMv8.4-PMU and STALL_SLOT event are > implemented, it returns the slots from PMMIR_EL1, otherwise it will > return 0. We check for the STALL_SLOT event becuase (at the time) the ARM ARM said: | If STALL_SLOT is not implemented, it is IMPLEMENTATION DEFINED whether the | PMMIR System registers are implemented. ... and this was necessary to avoid triggering an UNDEFINED exception if we attempted to read PMMIR on a CPU which didn't actually implement it. See: https://lore.kernel.org/linux-arm-kernel/20200720101518.GA11516@willie-the-truck/ https://lore.kernel.org/linux-arm-kernel/20200720105019.GA54220@C02TD0UTHF1T.local/ https://lore.kernel.org/linux-arm-kernel/20200720105410.GD11516@willie-the-truck/ As I promised in that thread, I did raise that with our architects. According to the bug I filed against the architecture, this was tightened such that ARMv8.4-PMU gauaranteed the presence of PMMIR, and that should have changed between the G.a and G.b releases of the ARM ARM. Anshuman, can you go and check that the wording did chaange between G.a and G.b? Assuming it did (and the wording in the latest J.a release is also fine), please update the commit message to describe the history above. Thanks, Mark.