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Date:   Thu, 12 Oct 2023 13:03:43 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Jon Hunter <jonathanh@nvidia.com>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
        Johnny Liu <johnliu@nvidia.com>,
        Ankur Pawar <ankurp@nvidia.com>
Subject: Re: [PATCH] memory: tegra: Add Tegra234 clients for RCE and VI
Message-ID: <ZSfSj42AXcnI895C@orome.fritz.box>
References: <20231012104909.48518-1-jonathanh@nvidia.com>
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On Thu, Oct 12, 2023 at 11:49:09AM +0100, Jon Hunter wrote:
> Add the Tegra234 memory client entries for the Real-time Camera Engine
> (RCE) and Video Input (VI) devices.
>=20
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
>  drivers/memory/tegra/tegra234.c | 60 +++++++++++++++++++++++++++++++++
>  1 file changed, 60 insertions(+)

Krzysztof,

again, let me know how you want to handle this. I can pick it up into
the Tegra tree along with Sumit's 2-patch series, or you can take these
if you prefer, in which case:

Acked-by: Thierry Reding <treding@nvidia.com>

>=20
> diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra=
234.c
> index 9e5b5dbd9c8d..42c79f9a70af 100644
> --- a/drivers/memory/tegra/tegra234.c
> +++ b/drivers/memory/tegra/tegra234.c
> @@ -449,6 +449,18 @@ static const struct tegra_mc_client tegra234_mc_clie=
nts[] =3D {
>  				.security =3D 0x38c,
>  			},
>  		},
> +	}, {
> +		.id =3D TEGRA234_MEMORY_CLIENT_VIW,
> +		.name =3D "viw",
> +		.bpmp_id =3D TEGRA_ICC_BPMP_VI,
> +		.type =3D TEGRA_ICC_ISO_VI,
> +		.sid =3D TEGRA234_SID_ISO_VI,
> +		.regs =3D {
> +			.sid =3D {
> +				.override =3D 0x390,
> +				.security =3D 0x394,
> +			},
> +		},
>  	}, {
>  		.id =3D TEGRA234_MEMORY_CLIENT_NVDECSRD,
>  		.name =3D "nvdecsrd",
> @@ -621,6 +633,30 @@ static const struct tegra_mc_client tegra234_mc_clie=
nts[] =3D {
>  				.security =3D 0x50c,
>  			},
>  		},
> +	}, {
> +		.id =3D TEGRA234_MEMORY_CLIENT_VIFALR,
> +		.name =3D "vifalr",
> +		.bpmp_id =3D TEGRA_ICC_BPMP_VIFAL,
> +		.type =3D TEGRA_ICC_ISO_VIFAL,
> +		.sid =3D TEGRA234_SID_ISO_VIFALC,
> +		.regs =3D {
> +			.sid =3D {
> +				.override =3D 0x5e0,
> +				.security =3D 0x5e4,
> +			},
> +		},
> +	}, {
> +		.id =3D TEGRA234_MEMORY_CLIENT_VIFALW,
> +		.name =3D "vifalw",
> +		.bpmp_id =3D TEGRA_ICC_BPMP_VIFAL,
> +		.type =3D TEGRA_ICC_ISO_VIFAL,
> +		.sid =3D TEGRA234_SID_ISO_VIFALC,
> +		.regs =3D {
> +			.sid =3D {
> +				.override =3D 0x5e8,
> +				.security =3D 0x5ec,
> +			},
> +		},
>  	}, {
>  		.id =3D TEGRA234_MEMORY_CLIENT_DLA0RDA,
>  		.name =3D "dla0rda",
> @@ -701,6 +737,30 @@ static const struct tegra_mc_client tegra234_mc_clie=
nts[] =3D {
>  				.security =3D 0x62c,
>  			},
>  		},
> +	}, {
> +		.id =3D TEGRA234_MEMORY_CLIENT_RCER,
> +		.name =3D "rcer",
> +		.bpmp_id =3D TEGRA_ICC_BPMP_RCE,
> +		.type =3D TEGRA_ICC_NISO,
> +		.sid =3D TEGRA234_SID_RCE,
> +		.regs =3D {
> +			.sid =3D {
> +				.override =3D 0x690,
> +				.security =3D 0x694,
> +			},
> +		},
> +	}, {
> +		.id =3D TEGRA234_MEMORY_CLIENT_RCEW,
> +		.name =3D "rcew",
> +		.bpmp_id =3D TEGRA_ICC_BPMP_RCE,
> +		.type =3D TEGRA_ICC_NISO,
> +		.sid =3D TEGRA234_SID_RCE,
> +		.regs =3D {
> +			.sid =3D {
> +				.override =3D 0x698,
> +				.security =3D 0x69c,
> +			},
> +		},
>  	}, {
>  		.id =3D TEGRA234_MEMORY_CLIENT_PCIE0R,
>  		.name =3D "pcie0r",
> --=20
> 2.34.1
>=20

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