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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id bb36-20020a05622a1b2400b00403ad6ec2e8sm6182191qtb.26.2023.10.12.06.46.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Oct 2023 06:46:29 -0700 (PDT) Message-ID: <4c73e58f-13d3-7cb9-a706-b20ab7d2df18@redhat.com> Date: Thu, 12 Oct 2023 15:46:26 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Reply-To: eric.auger@redhat.com Subject: Re: [PATCH v3 2/3] arm64: Add missing _EL2 encodings Content-Language: en-US To: Miguel Luis , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Jing Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev References: <20231011180103.91774-1-miguel.luis@oracle.com> <20231011180103.91774-3-miguel.luis@oracle.com> From: Eric Auger In-Reply-To: <20231011180103.91774-3-miguel.luis@oracle.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 12 Oct 2023 06:47:31 -0700 (PDT) Hi Miguel, On 10/11/23 20:01, Miguel Luis wrote: > Some _EL2 encodings are missing. Add them. > > Signed-off-by: Miguel Luis Reviewed-by: Eric Auger Eric > --- > arch/arm64/include/asm/sysreg.h | 37 +++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index ba5db50effec..d8e8607c9de8 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -484,6 +484,7 @@ > > #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) > #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) > +#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) > #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) > #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) > #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) > @@ -497,6 +498,10 @@ > #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) > > #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) > +#define SYS_SDER32_EL2 sys_reg(3, 4, 1, 3, 1) > +#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) > +#define SYS_VSTTBR_EL2 sys_reg(3, 4, 2, 6, 0) > +#define SYS_VSTCR_EL2 sys_reg(3, 4, 2, 6, 2) > #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) > #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) > #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) > @@ -514,6 +519,18 @@ > > #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) > #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) > +#define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0) > +#define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1) > +#define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0) > +#define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x) > +#define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0) > +#define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1) > +#define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2) > +#define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3) > +#define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4) > +#define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5) > +#define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6) > +#define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7) > > #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) > #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) > @@ -562,9 +579,29 @@ > > #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) > #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) > +#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7) > + > +#define __AMEV_op2(m) (m & 0x7) > +#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) > +#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m)) > +#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m) > +#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m)) > +#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m) > > #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) > #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) > +#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0) > +#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1) > +#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2) > +#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0) > +#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1) > +#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) > +#define SYS_CNTHVS_TVAL_EL2 sys_reg(3, 4, 14, 4, 0) > +#define SYS_CNTHVS_CTL_EL2 sys_reg(3, 4, 14, 4, 1) > +#define SYS_CNTHVS_CVAL_EL2 sys_reg(3, 4, 14, 4, 2) > +#define SYS_CNTHPS_TVAL_EL2 sys_reg(3, 4, 14, 5, 0) > +#define SYS_CNTHPS_CTL_EL2 sys_reg(3, 4, 14, 5, 1) > +#define SYS_CNTHPS_CVAL_EL2 sys_reg(3, 4, 14, 5, 2) > > /* VHE encodings for architectural EL0/1 system registers */ > #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)