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Message-ID: <fe4da875-36d4-4eeb-ba83-8c24899c9097@linaro.org>
Date:   Thu, 12 Oct 2023 18:59:48 +0200
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Subject: Re: [PATCH v4 1/3] arm64: dts: qcom: Add interconnect nodes for SDX75
Content-Language: en-US
To:     Rohit Agarwal <quic_rohiagar@quicinc.com>, agross@kernel.org,
        andersson@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        dmitry.baryshkov@linaro.org
Cc:     linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <1696406908-9688-1-git-send-email-quic_rohiagar@quicinc.com>
 <1696406908-9688-2-git-send-email-quic_rohiagar@quicinc.com>
 <3a042a26-81b4-4ab3-ba03-a38ae876634b@linaro.org>
 <6da8dc86-0b9a-488f-9046-9d9d269beeaf@quicinc.com>
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <6da8dc86-0b9a-488f-9046-9d9d269beeaf@quicinc.com>
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On 10/12/23 18:57, Rohit Agarwal wrote:
> 
> On 10/12/2023 10:18 PM, Konrad Dybcio wrote:
>>
>>
>> On 10/4/23 10:08, Rohit Agarwal wrote:
>>> Add interconnect nodes to support interconnects on SDX75.
>>> Also parallely add the interconnect property for UART required
>>> so that the bootup to shell does not break with interconnects
>>> in place.
>>>
>>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 
>>> +++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 52 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi 
>>> b/arch/arm64/boot/dts/qcom/sdx75.dtsi
>>> index e180aa4..b4723fa 100644
>>> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
>>> @@ -8,6 +8,8 @@
>>>     #include <dt-bindings/clock/qcom,rpmh.h>
>>>   #include <dt-bindings/clock/qcom,sdx75-gcc.h>
>>> +#include <dt-bindings/interconnect/qcom,icc.h>
>>> +#include <dt-bindings/interconnect/qcom,sdx75.h>
>>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>   #include <dt-bindings/power/qcom,rpmhpd.h>
>>>   #include <dt-bindings/power/qcom-rpmpd.h>
>>> @@ -203,6 +205,19 @@
>>>           };
>>>       };
>>>   +    clk_virt: interconnect-0 {
>>> +        compatible = "qcom,sdx75-clk-virt";
>>> +        #interconnect-cells = <2>;
>>> +        qcom,bcm-voters = <&apps_bcm_voter>;
>>> +        clocks = <&rpmhcc RPMH_QPIC_CLK>;
>>> +    };
>>> +
>>> +    mc_virt: interconnect-1 {
>>> +        compatible = "qcom,sdx75-mc-virt";
>>> +        #interconnect-cells = <2>;
>>> +        qcom,bcm-voters = <&apps_bcm_voter>;
>>> +    };
>>> +
>>>       memory@80000000 {
>>>           device_type = "memory";
>>>           reg = <0x0 0x80000000 0x0 0x0>;
>>> @@ -434,6 +449,9 @@
>>>               clock-names = "m-ahb",
>>>                         "s-ahb";
>>>               iommus = <&apps_smmu 0xe3 0x0>;
>>> +            interconnects = <&clk_virt MASTER_QUP_CORE_0 
>>> QCOM_ICC_TAG_ALWAYS
>>> +                     &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
>>> +            interconnect-names = "qup-core";
>> No qup-config?
>>
>> My brain compiler says this would cause a dt checker warning, at least 
>> on next-20231012.
> If I check the tip, then there is only one interconnect entry.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/soc/qcom/qcom%2Cgeni-se.yaml#L50
> For the debug uart, the qup-config is added.
> I did check the dtbs_check before sending these patches.
> Please let me know if I am missing anything.
Oh, my brain compiler was correct, but for the wrong input data :)

I thought you added this property to the UART itself, not to the QUP 
controller. Yes, you're right.

Konrad