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Message-ID: <420f9132-b277-4476-bd74-9cc4cd87456f@linaro.org>
Date:   Fri, 13 Oct 2023 09:06:35 +0200
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Subject: Re: [PATCH 3/4] arm64: dts: nuvoton: Add pinctrl support for ma35d1
Content-Language: en-US
To:     Jacky Huang <ychuang570808@gmail.com>, linus.walleij@linaro.org,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, p.zabel@pengutronix.de, j.neuschaefer@gmx.net
Cc:     linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        schung@nuvoton.com, Jacky Huang <ychuang3@nuvoton.com>
References: <20231011090510.114476-1-ychuang570808@gmail.com>
 <20231011090510.114476-4-ychuang570808@gmail.com>
 <9a831a6e-ab5e-4911-8011-f6eb82dd3d6a@linaro.org>
 <507e491a-e40f-47e2-8e11-5a7886a8c2ab@gmail.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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On 13/10/2023 08:52, Jacky Huang wrote:
>>> +
>>> +&pinctrl {
>>> +	uart0 {
>>> +		pinctrl_uart0: uart0grp {
>>> +			nuvoton,pins =
>>> +				<MA35_SYS_REG_GPE_H 24 1 &pcfg_default>,
>>> +				<MA35_SYS_REG_GPE_H 28 1 &pcfg_default>;
>> This does not look like generic pinctrl bindings. Looks
>> over-complicated. From where did you get it? Which recent bindings and
>> drivers where used as an example? Register addresses should be in the
>> driver. Bit offsets as well. "multi-pin-function-value" confuses me. All
>> this is not really suitable for DTS.
> 
> Okay, I will update the first and second items to 'pin bank' and 'pin 
> bank index,
> just as others have done, and leave the driver to handle the conversion into
> registers and offsets.

Instead use existing common properties, like "pins" and "groups" (or
pinmux).

> 
> The term "multi-pin-function-value" is used to specify the device function.
> I will use the name "device function" instead of "multi-pin-function-value.

Use existing common properties, like "function". Do not reinvent the
bindings.


Best regards,
Krzysztof