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X-IronPort-AV: E=McAfee;i="6600,9927,10862"; a="375552697" X-IronPort-AV: E=Sophos;i="6.03,222,1694761200"; d="scan'208";a="375552697" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2023 08:06:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10862"; a="704676500" X-IronPort-AV: E=Sophos;i="6.03,222,1694761200"; d="scan'208";a="704676500" Received: from marinjul-mobl.amr.corp.intel.com (HELO [10.255.231.41]) ([10.255.231.41]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2023 08:06:00 -0700 Content-Type: multipart/mixed; boundary="------------4QAAwMnZ7myaM0IpTAN94Ja9" Message-ID: <532fd5c3-dddb-4503-9b81-31c3d07a7119@intel.com> Date: Fri, 13 Oct 2023 08:05:54 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/12] x86/mce: Fix hw MCE injection feature detection Content-Language: en-US To: isaku.yamahata@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@gmail.com, Michael Roth , Paolo Bonzini , Sean Christopherson , linux-coco@lists.linux.dev, Chao Peng , Smita Koralahalli , Borislav Petkov References: <23c6fa20777498bccd486aedc435eef9af174748.1696926843.git.isaku.yamahata@intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Fri, 13 Oct 2023 08:06:10 -0700 (PDT) This is a multi-part message in MIME format. --------------4QAAwMnZ7myaM0IpTAN94Ja9 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Isaku, when you report a bug, it would be great to include the folks who authored and worked on the original patch that introduced the bug. I've gone ahead and done that for you here. On 10/10/23 01:35, isaku.yamahata@intel.com wrote: > From: Isaku Yamahata > > When initializing x86 MCE injection framework, it checks if hardware mce > injection is available or not. When it's not available on AMD, set the > boolean variable to false to not use it. The variable is on by default and > the feature is AMD specific based on the code. > > Because the variable is default on, it is true on Intel platform (probably > on other non-AMD x86 platform). It results in unchecked msr access of > MSR_K7_HWCR=0xc0010015 when injecting MCE on Intel platform. (Probably on > other x86 platform.) > > Make the variable of by default, and set the variable on when the hardware > feature is usable. Gah, I'm finding that changelog impenetrable. Here's what's missing: * The entirety of check_hw_inj_possible() is for AMD hardware: X86_FEATURE_SMCA, the MSRs, hw_injection_possible, everything. * Only AMD systems with SMCA support hardware error injection (anything other than "echo sw > /sys/kernel/debug/mce-inject/flags") * That AMD-only restriction is enforced by 'hw_injection_possible' * 'hw_injection_possible' is true by default and only set to false in check_hw_inj_possible() ... the AMD-only code The end result is that everyone except SMCA-enabled AMD systems (Intel included) leaves hw_injection_possible=true. They are free to try and inject hardware errors. If they do, they'll get errors when writing to the MSRs. To fix this, make disable hw_injection_possible by default. Only enable it on SMCA hardware that actually succeeds in ... whatever: wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status); rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status); is doing. ... and don't do it at the top of the function. Why bother setting it to true only to disable it a moment later? Do something like the following instead. --------------4QAAwMnZ7myaM0IpTAN94Ja9 Content-Type: text/x-patch; charset=UTF-8; name="amdmce.patch" Content-Disposition: attachment; filename="amdmce.patch" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNlL2luamVjdC5jIGIvYXJjaC94 ODYva2VybmVsL2NwdS9tY2UvaW5qZWN0LmMKaW5kZXggNGQ4ZDRiY2Y5MTVkLi4wMWVlODg2 ZDg1NDAgMTAwNjQ0Ci0tLSBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNlL2luamVjdC5jCisr KyBiL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNlL2luamVjdC5jCkBAIC0zMyw3ICszMyw3IEBA CiAKICNpbmNsdWRlICJpbnRlcm5hbC5oIgogCi1zdGF0aWMgYm9vbCBod19pbmplY3Rpb25f cG9zc2libGUgPSB0cnVlOworc3RhdGljIGJvb2wgaHdfaW5qZWN0aW9uX3Bvc3NpYmxlOwog CiAvKgogICogQ29sbGVjdCBhbGwgdGhlIE1DaV9YWFggc2V0dGluZ3MKQEAgLTc0OCw5ICs3 NDgsMTAgQEAgc3RhdGljIHZvaWQgY2hlY2tfaHdfaW5qX3Bvc3NpYmxlKHZvaWQpCiAJCXJk bXNybF9zYWZlKG1jYV9tc3JfcmVnKGJhbmssIE1DQV9TVEFUVVMpLCAmc3RhdHVzKTsKIAog CQlpZiAoIXN0YXR1cykgewotCQkJaHdfaW5qZWN0aW9uX3Bvc3NpYmxlID0gZmFsc2U7CiAJ CQlwcl93YXJuKCJQbGF0Zm9ybSBkb2VzIG5vdCBhbGxvdyAqaGFyZHdhcmUqIGVycm9yIGlu amVjdGlvbi4iCiAJCQkJIlRyeSB1c2luZyBBUEVJIEVJTkogaW5zdGVhZC5cbiIpOworCQl9 IGVsc2UgeworCQkJaHdfaW5qZWN0aW9uX3Bvc3NpYmxlID0gdHJ1ZTsKIAkJfQogCiAJCXRv Z2dsZV9od19tY2VfaW5qZWN0KGNwdSwgZmFsc2UpOwo= --------------4QAAwMnZ7myaM0IpTAN94Ja9--