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Received: from MN2PR12MB3407.namprd12.prod.outlook.com (2603:10b6:208:c5::18) by DS0PR12MB8480.namprd12.prod.outlook.com (2603:10b6:8:159::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.44; Fri, 13 Oct 2023 15:36:10 +0000 Received: from MN2PR12MB3407.namprd12.prod.outlook.com ([fe80::3008:be4:e9a4:2a98]) by MN2PR12MB3407.namprd12.prod.outlook.com ([fe80::3008:be4:e9a4:2a98%7]) with mapi id 15.20.6863.043; Fri, 13 Oct 2023 15:36:10 +0000 Message-ID: Date: Fri, 13 Oct 2023 16:36:06 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1 master and MAINTAINERS entry To: Krzysztof Kozlowski , Conor Dooley Cc: thomas.delev@amd.com, michal.simek@amd.com, robh+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, git@amd.com References: <20231013093109.37165-1-kris.chaplin@amd.com> <20231013093109.37165-2-kris.chaplin@amd.com> <20231013-january-caliber-2e7acbee15ec@spud> <6fa74ee3-a2ef-4d76-964f-51249f53cbaa@linaro.org> From: Kris Chaplin In-Reply-To: <6fa74ee3-a2ef-4d76-964f-51249f53cbaa@linaro.org> Content-Type: text/plain; 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Fri, 13 Oct 2023 08:36:29 -0700 (PDT) On 13/10/2023 16:29, Krzysztof Kozlowski wrote: > > AMD product managers are highly skilled in naming things. Sigh. > > Go ahead with AXI 1-wire master. Any future - from now to next 100 years > - product from AMD which will be different but sold under the same name, > thus creating conflict in compatible naming, should be rejected because > of that conflict or renamed to something else. If that happen I will > propose a name like "banana-wire". > > Best regards, > Krzysztof To be fair on the product managers the IP naming from a hardware perspective is in the context of the ex-Xilinx development tools, and as such there is no risk of namespace overlap with the rest of the business.  I'm not against changing the binding name for clarity in the kernel. Would adding pl within the binding (Programmable Logic) assist? Ie: amd,pl-axi-1wire-master Regards Kris