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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697211718; x=1697816518; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=58F4pC3mBDu8F+pvcYNIm1FByUJEAPva6M9hCs3f/vs=; b=RqfVYdZjbAl2wVfWtP4/CFJZHAlZKB4XmJKlBkkXD6yh5examero+LHn4sQPWsk8Ie iCgrgRzxFOjmJqFoS2Rk+CG2tu1xdflSb9wdsMniQhyPS09KWfRFiDyo78AgY3bDKmb7 FCnhooKQy+Ntm511NkMsKQXiyQofgBn2615kCBYtDwIchqrTtUMX2jwkqYGGg2fJK0vk ZtyYfdzDpJ5Jw1NMeG+MH/Ax/Ni9EAWTZ5+bLI/vlQTg5ksL7NSTIB1LLGITTypu/IPH 58Duc6/ltovPtcJuNn8S+KLhAOowfvLzwkHqeJS1m7kvzrpIlwcMepJnqIgEz6DCSN6b +nlg== X-Gm-Message-State: AOJu0YxKGpf6IiqFxuDh9ljGJFN/c5coOCMtHAOru7I/94Nm2DoIFJJj vUMoqMlxUgJkQo0eiUB6UCfMG0MnYGpiXohGEPUgoQ== X-Received: by 2002:a05:6870:6587:b0:1e9:b7a7:8efe with SMTP id fp7-20020a056870658700b001e9b7a78efemr5211668oab.2.1697211718067; Fri, 13 Oct 2023 08:41:58 -0700 (PDT) MIME-Version: 1.0 References: <20231012051509.738750-1-apatel@ventanamicro.com> <20231012051509.738750-8-apatel@ventanamicro.com> <87fs2ghxyz.fsf@all.your.base.are.belong.to.us> In-Reply-To: <87fs2ghxyz.fsf@all.your.base.are.belong.to.us> From: Anup Patel Date: Fri, 13 Oct 2023 21:11:46 +0530 Message-ID: Subject: Re: [PATCH v2 7/8] tty: Add SBI debug console support to HVC SBI driver To: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Atish Patra Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 13 Oct 2023 08:42:23 -0700 (PDT) On Thu, Oct 12, 2023 at 5:08=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel wrote: > > Anup Patel writes: > > > From: Atish Patra > > > > RISC-V SBI specification supports advanced debug console > > support via SBI DBCN extension. > > > > Extend the HVC SBI driver to support it. > > > > Signed-off-by: Atish Patra > > Signed-off-by: Anup Patel > > --- > > drivers/tty/hvc/Kconfig | 2 +- > > drivers/tty/hvc/hvc_riscv_sbi.c | 76 ++++++++++++++++++++++++++++++--- > > 2 files changed, 70 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig > > index 4f9264d005c0..6e05c5c7bca1 100644 > > --- a/drivers/tty/hvc/Kconfig > > +++ b/drivers/tty/hvc/Kconfig > > @@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP > > > > config HVC_RISCV_SBI > > bool "RISC-V SBI console support" > > - depends on RISCV_SBI_V01 > > + depends on RISCV_SBI > > select HVC_DRIVER > > help > > This enables support for console output via RISC-V SBI calls, w= hich > > diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_risc= v_sbi.c > > index 31f53fa77e4a..da318d7f55c5 100644 > > --- a/drivers/tty/hvc/hvc_riscv_sbi.c > > +++ b/drivers/tty/hvc/hvc_riscv_sbi.c > > @@ -39,21 +39,83 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *= buf, int count) > > return i; > > } > > > > -static const struct hv_ops hvc_sbi_ops =3D { > > +static const struct hv_ops hvc_sbi_v01_ops =3D { > > .get_chars =3D hvc_sbi_tty_get, > > .put_chars =3D hvc_sbi_tty_put, > > }; > > > > -static int __init hvc_sbi_init(void) > > +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int= count) > > { > > - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16)); > > + phys_addr_t pa; > > + struct sbiret ret; > > + > > + if (is_vmalloc_addr(buf)) > > + pa =3D page_to_phys(vmalloc_to_page(buf)) + offset_in_pag= e(buf); > > What is assumed from buf here? If buf is crossing a page, you need to > adjust the count, no? I never saw a page crossing buffer but I will certainly address this in the next revision. > > > + else > > + pa =3D __pa(buf); > > + > > + if (IS_ENABLED(CONFIG_32BIT)) > > + ret =3D sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRIT= E, > > + count, lower_32_bits(pa), upper_32_bits(p= a), > > + 0, 0, 0); > > + else > > + ret =3D sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRIT= E, > > + count, pa, 0, 0, 0, 0); > > + if (ret.error) > > + return 0; > > + > > + return count; > > } > > -device_initcall(hvc_sbi_init); > > > > -static int __init hvc_sbi_console_init(void) > > +static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count= ) > > { > > - hvc_instantiate(0, 0, &hvc_sbi_ops); > > + phys_addr_t pa; > > + struct sbiret ret; > > + > > + if (is_vmalloc_addr(buf)) > > + pa =3D page_to_phys(vmalloc_to_page(buf)) + offset_in_pag= e(buf); > > And definitely adjust count here, if we're crossing a page! Sure, I will update here as well. Thanks, Anup