Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31;
Date:   Fri, 13 Oct 2023 12:18:22 -0500
From:   Rob Herring <robh@kernel.org>
To:     Kris Chaplin <kris.chaplin@amd.com>
Cc:     Conor Dooley <conor@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        thomas.delev@amd.com, michal.simek@amd.com, conor+dt@kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        git@amd.com
Subject: Re: [PATCH 1/2] dt-bindings: w1: Add YAML DT Schema for AMD w1
 master and MAINTAINERS entry
Message-ID: <20231013171822.GA4177785-robh@kernel.org>
References: <20231013093109.37165-1-kris.chaplin@amd.com>
 <20231013093109.37165-2-kris.chaplin@amd.com>
 <f864dd17-7848-4a83-bd8b-2093d11a153a@linaro.org>
 <20231013-january-caliber-2e7acbee15ec@spud>
 <c58fbddb-cda1-e0de-8ad9-e4701c2c73cb@amd.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <c58fbddb-cda1-e0de-8ad9-e4701c2c73cb@amd.com>
Precedence: bulk

On Fri, Oct 13, 2023 at 04:23:15PM +0100, Kris Chaplin wrote:
> 
> On 13/10/2023 16:07, Conor Dooley wrote:
> > On Fri, Oct 13, 2023 at 05:04:32PM +0200, Krzysztof Kozlowski wrote:
> > > 
> > > That's a quite generic compatible. axi is ARM term, 1-wire is the name
> > > of the bus and master is the role. Concatenating three common words does
> > > not create unique device name. Compatibles are supposed to be specific
> > > and this is really relaxed. Anything can be over AXI, everything in
> > > 1wire is 1wire and every master device is a master.
> > Given the vendor (and the title of the binding) this is almost certainly
> > an FPGA IP core, so the generic name is understandable. Using the exact
> > name of the IP in the AMD/Xilinx catalog probably is the best choice?
> 
> Indeed this is an Programmable Logic IP core - the official name of the core
> in our catalog is axi_1wire_master.? It is a soft HDL core.

Only 1 version of it (ever)? Like other PL IP, it needs a version number 
(and not v1, v2, etc. made up by you). Really, your versioning scheme 
should be documented (like 
bindings/sifive/sifive-blocks-ip-versioning.txt), but Xilinx started 
versioning stuff some time back.

Also, 'master' is not considered great terminology nowadays. Perhaps the 
catalog name should be updated. 

Rob