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From:   Ashish Kalra <Ashish.Kalra@amd.com>
To:     <dave.hansen@linux.intel.com>, <luto@kernel.org>,
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        <linux-kernel@vger.kernel.org>, <peterz@infradead.org>
Subject: [PATCH] x86/mm: fix pg_level_to_pfn for 5-level paging mode.
Date:   Fri, 13 Oct 2023 19:17:03 +0000
Message-ID: <20231013191703.422085-1-Ashish.Kalra@amd.com>
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From: Ashish Kalra <ashish.kalra@amd.com>

Add support for 5-level paging in pg_level_to_pfn().

Signed-off-by: Ashish Kalra <ashish.kalra@amd.com>
---
 arch/x86/mm/mem_encrypt_amd.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c
index 6faea41e99b6..45914568596a 100644
--- a/arch/x86/mm/mem_encrypt_amd.c
+++ b/arch/x86/mm/mem_encrypt_amd.c
@@ -267,6 +267,10 @@ static unsigned long pg_level_to_pfn(int level, pte_t *kpte, pgprot_t *ret_prot)
 		pfn = pud_pfn(*(pud_t *)kpte);
 		prot = pud_pgprot(*(pud_t *)kpte);
 		break;
+	case PG_LEVEL_512G:
+		pfn = p4d_pfn(*(p4d_t *)kpte);
+		prot = p4d_pgprot(*(p4d_t *)kpte);
+		break;
 	default:
 		WARN_ONCE(1, "Invalid level for kpte\n");
 		return 0;
-- 
2.25.1