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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id ob2-20020a17090b390200b0027740943ec2si1038067pjb.158.2023.10.13.15.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 15:01:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=KYvvVIrF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 4D90F828CC19; Fri, 13 Oct 2023 15:01:25 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231814AbjJMWBU (ORCPT + 99 others); Fri, 13 Oct 2023 18:01:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229632AbjJMWBT (ORCPT ); Fri, 13 Oct 2023 18:01:19 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A5FCB7; Fri, 13 Oct 2023 15:01:17 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC245C433C7; Fri, 13 Oct 2023 22:01:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697234476; bh=eN7+8Uo6JxL07H1+Tga+pr6b8+j6RjcgOEu8xBzIYig=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=KYvvVIrF5//SG+aOAPpO3yWmmp1TqkuMIlU8WxVNmZDEhYWdtuFm+6kba3N9CE9Cq jLFWe4Rhl7nhpLf/wx/PxCClh+kbhGuuIIT+ModtT7r1iAZoqO5OVh1m8GkUoTdreA uyfODD467MPyXEHr97OmwdZC3cO3m0xV2bbhUlLXeSVp9CN9o4/Gd2eGIsegyw0m7U uvDmAhJSP7k9uEf45oWh5agWBwdIm6/5Ju0ponf+KoPFpNAzKCoONa+U27g+KAyJgd MwpfyNG1UXXA1tCMSRQ/t+spLCiEfrKM/5meejxctbynQvm2IphlygNupZ6VHp6VbJ Dihkm/p62bC4w== Message-ID: <2fb931d1aa2190b918d0ddba87579eeb.sboyd@kernel.org> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <1jmswnvub2.fsf@starbuckisacylon.baylibre.com> References: <20231010062917.3624223-1-xianwei.zhao@amlogic.com> <20231010062917.3624223-5-xianwei.zhao@amlogic.com> <5e0bd4bba88701dd1a7a3e89d18412f0.sboyd@kernel.org> <1jmswnvub2.fsf@starbuckisacylon.baylibre.com> Subject: Re: [PATCH V2 4/4] clk: meson: c3: add c3 clock peripherals controller driver From: Stephen Boyd Cc: Neil Armstrong , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Kevin Hilman , Martin Blumenstingl , Chuan Liu To: Jerome Brunet , Xianwei Zhao , devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 13 Oct 2023 15:01:14 -0700 User-Agent: alot/0.10 X-Spam-Status: No, score=-1.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 13 Oct 2023 15:01:25 -0700 (PDT) Quoting Jerome Brunet (2023-10-13 00:38:14) >=20 > On Thu 12 Oct 2023 at 16:51, Stephen Boyd wrote: >=20 > > Quoting Xianwei Zhao (2023-10-09 23:29:17) > >> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig > >> index 76be4bbd2afb..c8d59d28c8ff 100644 > >> --- a/drivers/clk/meson/Kconfig > >> +++ b/drivers/clk/meson/Kconfig > >> @@ -140,6 +140,19 @@ config COMMON_CLK_C3_PLL > >> Say Y if you want the board to work, because PLLs are the pa= rent of most > >> peripherals. > >> =20 > >> +config COMMON_CLK_C3_PERIPHERALS > >> + tristate "Amlogic C3 peripherals clock controller" > >> + default y > > > > Why are these default y? They should depend on something like ARM64 and > > even then I don't see why we want to enable them by default if we're > > building the ARM64 kernel. >=20 > Should indeed depend on ARM64. Cool. >=20 > Those are the main clock controllers. Like for other AML SoC families, > they are necessary to boot the device which is why they use 'default y' >=20 > Is it a problem ? >=20 > The whole meson directory depends on ARCH_MESON, so the drivers will go > away if Amlogic support is removed on ARM64. No it isn't a problem if the entire section is implicitly depending on ARCH_MESON.