Received: by 2002:a05:7412:d8a:b0:e2:908c:2ebd with SMTP id b10csp1619045rdg; Sat, 14 Oct 2023 09:16:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGIoG1nMZqChcCafuMsKga6Az3OF/VR/MBfd/Uzw1SlidI4Z36F6UkrehYELnEToV1MDT+U X-Received: by 2002:a05:6a20:42a3:b0:16b:8132:b547 with SMTP id o35-20020a056a2042a300b0016b8132b547mr24347399pzj.4.1697300196210; Sat, 14 Oct 2023 09:16:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697300196; cv=none; d=google.com; s=arc-20160816; b=Heg0uPALh7XYUS+Mk5dsV8wldkJBYskItJcZhNCiNl6Z6wfZY3VG1ABc7T7sN0KI16 Nt5tcfgAoMgWuNOlh9uzmMVI0uaNFi4wusEgAcoxjujTtECkC4VjSsP1YGVe4mkfgzSa r1EMMETV2UUrAuQNoHpRtGnBROHFApfgE/dZq3I1+Y21ptVQnCtcx+rp3LEp4QbMnOuL +eWQvPaeIZ4GiYxtSb22xV9HS7dC43tyR/xig5mtdR6/OYdi8i/cFVAQ9E0XTl86f9LQ ZQjMaMwR2iqEfgflMTgFnbjGda+eVD0Le5BuOQ3p6x2Qmg1VjOi9fhXyvwLQfbzkOxer JQYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:subject:cc:to:from:date :dkim-signature; bh=6kriMAwjULcFTFFkkOfYSTzObbzKcPrHqPGaq7LDDX4=; fh=8qRmchecXqrC8iW4nNheQN28QLx+nVPb5KpKaabxzMY=; b=MLDFZg0f3Cr+m7ZZPblBfFMpF4ssF4xZKZfi6EkDXUtyV1+o39v9y0Fpd5gw48vU8W k5sbBJ/e83QseHylSlc0ENVx/KehOtvrfh+DY7Zb6zx3/DgsNm7upwSih2Slrg7SkQFh VBGqwqyMTI6RQjb5DzYcx87qYBEgIXBASxkK7NHTzFW9NyN8mv9ihb5Ho29AWNfvTrq4 lpN+i6ua6zuh4MbqjKNwVsrovEeGJf/kpOeHEP/bqenZ5ci+Gv/0SG1m3DM/nem1g/VC tXGaVlwl7dU77HoZptmPFuG4cCY0rj/hoXSbIz08/j8VOkhTI1Ybnr2r93jOjvcc2psP HddQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=X1EmAge9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id n11-20020a170902e54b00b001c9b15bf939si7544331plf.358.2023.10.14.09.16.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Oct 2023 09:16:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=X1EmAge9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 3A4238040EF8; Sat, 14 Oct 2023 09:16:23 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233264AbjJNQQK (ORCPT + 99 others); Sat, 14 Oct 2023 12:16:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230211AbjJNQQJ (ORCPT ); Sat, 14 Oct 2023 12:16:09 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50C4AA2; Sat, 14 Oct 2023 09:16:06 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA56AC433C8; Sat, 14 Oct 2023 16:16:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697300166; bh=bloyWWM50cgSdXW/M/ONp1t9BKdvFll8JAVkflss0qk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=X1EmAge9ScIen7JtkLBWghNUQoZoy6NrdY9FNXqGPKimSOb8r1kTs7tfdeHZNPfu/ RNDhoI+VmRsexi0e0SXt+tc9EIjIPw60d/r6XV28LspIuwRUvGBI3kd8QaKzeGm5xO hc/5VkpxH39bziNl07SEOdU0vq5RzDq1C+FQf1b2uytuIYtSFAbraSQ6PvaYPMD+Pn fDZIA1nVe7FPGRpjsmAY+UsrMBb+u1HJKuhcDz0z/XmCgGRHTvAA2+eIWNZkz3ZVvN EKkF8OvaUP1rPC18c8k7C6IkJHXQOQepCuXFEWq/hN9YlRf09M9E5jQs+JwqPpkXfK ACSuaD8wHHS9w== Date: Sat, 14 Oct 2023 17:16:19 +0100 From: Jonathan Cameron To: Luca Weiss Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 1/4] iio: adc: Add PM7325 PMIC7 ADC bindings Message-ID: <20231014171619.7b7ea921@jic23-huawei> In-Reply-To: <20231013-fp5-thermals-v1-1-f14df01922e6@fairphone.com> References: <20231013-fp5-thermals-v1-0-f14df01922e6@fairphone.com> <20231013-fp5-thermals-v1-1-f14df01922e6@fairphone.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sat, 14 Oct 2023 09:16:23 -0700 (PDT) On Fri, 13 Oct 2023 10:09:53 +0200 Luca Weiss wrote: > Add the defines for the ADC channels found on the PM7325. The list is > taken from downstream msm-5.4 and adjusted for mainline. > > Signed-off-by: Luca Weiss I assume this will go with the dts changes that use it. Acked-by: Jonathan Cameron > --- > include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h | 69 +++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h > new file mode 100644 > index 000000000000..96908014e09e > --- /dev/null > +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h > @@ -0,0 +1,69 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2020 The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H > +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H > + > +#ifndef PM7325_SID > +#define PM7325_SID 1 > +#endif > + > +#include > + > +/* ADC channels for PM7325_ADC for PMIC7 */ > +#define PM7325_ADC7_REF_GND (PM7325_SID << 8 | ADC7_REF_GND) > +#define PM7325_ADC7_1P25VREF (PM7325_SID << 8 | ADC7_1P25VREF) > +#define PM7325_ADC7_VREF_VADC (PM7325_SID << 8 | ADC7_VREF_VADC) > +#define PM7325_ADC7_DIE_TEMP (PM7325_SID << 8 | ADC7_DIE_TEMP) > + > +#define PM7325_ADC7_AMUX_THM1 (PM7325_SID << 8 | ADC7_AMUX_THM1) > +#define PM7325_ADC7_AMUX_THM2 (PM7325_SID << 8 | ADC7_AMUX_THM2) > +#define PM7325_ADC7_AMUX_THM3 (PM7325_SID << 8 | ADC7_AMUX_THM3) > +#define PM7325_ADC7_AMUX_THM4 (PM7325_SID << 8 | ADC7_AMUX_THM4) > +#define PM7325_ADC7_AMUX_THM5 (PM7325_SID << 8 | ADC7_AMUX_THM5) > +#define PM7325_ADC7_GPIO1 (PM7325_SID << 8 | ADC7_GPIO1) > +#define PM7325_ADC7_GPIO2 (PM7325_SID << 8 | ADC7_GPIO2) > +#define PM7325_ADC7_GPIO3 (PM7325_SID << 8 | ADC7_GPIO3) > +#define PM7325_ADC7_GPIO4 (PM7325_SID << 8 | ADC7_GPIO4) > + > +/* 30k pull-up1 */ > +#define PM7325_ADC7_AMUX_THM1_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_30K_PU) > +#define PM7325_ADC7_AMUX_THM2_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_30K_PU) > +#define PM7325_ADC7_AMUX_THM3_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_30K_PU) > +#define PM7325_ADC7_AMUX_THM4_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_30K_PU) > +#define PM7325_ADC7_AMUX_THM5_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_30K_PU) > +#define PM7325_ADC7_GPIO1_30K_PU (PM7325_SID << 8 | ADC7_GPIO1_30K_PU) > +#define PM7325_ADC7_GPIO2_30K_PU (PM7325_SID << 8 | ADC7_GPIO2_30K_PU) > +#define PM7325_ADC7_GPIO3_30K_PU (PM7325_SID << 8 | ADC7_GPIO3_30K_PU) > +#define PM7325_ADC7_GPIO4_30K_PU (PM7325_SID << 8 | ADC7_GPIO4_30K_PU) > + > +/* 100k pull-up2 */ > +#define PM7325_ADC7_AMUX_THM1_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_100K_PU) > +#define PM7325_ADC7_AMUX_THM2_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_100K_PU) > +#define PM7325_ADC7_AMUX_THM3_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_100K_PU) > +#define PM7325_ADC7_AMUX_THM4_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_100K_PU) > +#define PM7325_ADC7_AMUX_THM5_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_100K_PU) > +#define PM7325_ADC7_GPIO1_100K_PU (PM7325_SID << 8 | ADC7_GPIO1_100K_PU) > +#define PM7325_ADC7_GPIO2_100K_PU (PM7325_SID << 8 | ADC7_GPIO2_100K_PU) > +#define PM7325_ADC7_GPIO3_100K_PU (PM7325_SID << 8 | ADC7_GPIO3_100K_PU) > +#define PM7325_ADC7_GPIO4_100K_PU (PM7325_SID << 8 | ADC7_GPIO4_100K_PU) > + > +/* 400k pull-up3 */ > +#define PM7325_ADC7_AMUX_THM1_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_400K_PU) > +#define PM7325_ADC7_AMUX_THM2_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_400K_PU) > +#define PM7325_ADC7_AMUX_THM3_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_400K_PU) > +#define PM7325_ADC7_AMUX_THM4_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_400K_PU) > +#define PM7325_ADC7_AMUX_THM5_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_400K_PU) > +#define PM7325_ADC7_GPIO1_400K_PU (PM7325_SID << 8 | ADC7_GPIO1_400K_PU) > +#define PM7325_ADC7_GPIO2_400K_PU (PM7325_SID << 8 | ADC7_GPIO2_400K_PU) > +#define PM7325_ADC7_GPIO3_400K_PU (PM7325_SID << 8 | ADC7_GPIO3_400K_PU) > +#define PM7325_ADC7_GPIO4_400K_PU (PM7325_SID << 8 | ADC7_GPIO4_400K_PU) > + > +/* 1/3 Divider */ > +#define PM7325_ADC7_GPIO4_DIV3 (PM7325_SID << 8 | ADC7_GPIO4_DIV3) > + > +#define PM7325_ADC7_VPH_PWR (PM7325_SID << 8 | ADC7_VPH_PWR) > + > +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H */ >