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Received: from TYZPR03MB6896.apcprd03.prod.outlook.com (2603:1096:400:289::14) by SEYPR03MB6578.apcprd03.prod.outlook.com (2603:1096:101:87::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.34; Mon, 16 Oct 2023 06:49:54 +0000 Received: from TYZPR03MB6896.apcprd03.prod.outlook.com ([fe80::792a:209d:4919:5db6]) by TYZPR03MB6896.apcprd03.prod.outlook.com ([fe80::792a:209d:4919:5db6%7]) with mapi id 15.20.6886.034; Mon, 16 Oct 2023 06:49:54 +0000 Message-ID: <05a5c068-6766-ade4-0e7c-e94b48c4d754@amlogic.com> Date: Mon, 16 Oct 2023 14:49:48 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH V2 4/4] clk: meson: c3: add c3 clock peripherals controller driver Content-Language: en-US To: Stephen Boyd , Jerome Brunet , devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Neil Armstrong , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Kevin Hilman , Martin Blumenstingl , Chuan Liu References: <20231010062917.3624223-1-xianwei.zhao@amlogic.com> <20231010062917.3624223-5-xianwei.zhao@amlogic.com> <5e0bd4bba88701dd1a7a3e89d18412f0.sboyd@kernel.org> <1jmswnvub2.fsf@starbuckisacylon.baylibre.com> <2fb931d1aa2190b918d0ddba87579eeb.sboyd@kernel.org> From: Xianwei Zhao In-Reply-To: <2fb931d1aa2190b918d0ddba87579eeb.sboyd@kernel.org> Content-Type: text/plain; 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Sun, 15 Oct 2023 23:50:53 -0700 (PDT) Hi Stephen & Jerome, Thanks for your reply. On 2023/10/14 06:01, Stephen Boyd wrote: > [ EXTERNAL EMAIL ] > > Quoting Jerome Brunet (2023-10-13 00:38:14) >> >> On Thu 12 Oct 2023 at 16:51, Stephen Boyd wrote: >> >>> Quoting Xianwei Zhao (2023-10-09 23:29:17) >>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig >>>> index 76be4bbd2afb..c8d59d28c8ff 100644 >>>> --- a/drivers/clk/meson/Kconfig >>>> +++ b/drivers/clk/meson/Kconfig >>>> @@ -140,6 +140,19 @@ config COMMON_CLK_C3_PLL >>>> Say Y if you want the board to work, because PLLs are the parent of most >>>> peripherals. >>>> >>>> +config COMMON_CLK_C3_PERIPHERALS >>>> + tristate "Amlogic C3 peripherals clock controller" >>>> + default y >>> >>> Why are these default y? They should depend on something like ARM64 and >>> even then I don't see why we want to enable them by default if we're >>> building the ARM64 kernel. >> >> Should indeed depend on ARM64. > > Cool. > Will add depend on ARM64 in next version. >> >> Those are the main clock controllers. Like for other AML SoC families, >> they are necessary to boot the device which is why they use 'default y' >> >> Is it a problem ? >> >> The whole meson directory depends on ARCH_MESON, so the drivers will go >> away if Amlogic support is removed on ARM64. > > No it isn't a problem if the entire section is implicitly depending on > ARCH_MESON.