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Date:   Mon, 16 Oct 2023 10:45:25 -0400
From:   Frank Li <Frank.li@nxp.com>
To:     Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc:     Minghuan Lian <minghuan.Lian@nxp.com>,
        Mingkai Hu <mingkai.hu@nxp.com>, Roy Zang <roy.zang@nxp.com>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Rob Herring <robh@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" 
        <linuxppc-dev@lists.ozlabs.org>,
        "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" 
        <linux-pci@vger.kernel.org>,
        "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" 
        <linux-arm-kernel@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>, imx@lists.linux.dev
Subject: Re: [PATCH 2/3] PCI: layerscape: add suspend/resume for ls1021a
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On Tue, Oct 10, 2023 at 06:02:36PM +0200, Lorenzo Pieralisi wrote:
> On Tue, Oct 10, 2023 at 10:20:12AM -0400, Frank Li wrote:
> > On Wed, Oct 04, 2023 at 10:23:51AM -0400, Frank Li wrote:
> > > On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> > > > ls1021a add suspend/resume support.
> > > > 
> > > > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > > > ---
> > > 
> > > ping
> > > 
> > > Frank
> > 
> > Ping
> 
> Read and follow please (and then ping us):
> https://lore.kernel.org/linux-pci/20171026223701.GA25649@bhelgaas-glaptop.roam.corp.google.com

Could you please help point which specic one was not follow aboved guide?
Then I can update my code. I think that's efficial communication method. I
think I have read it serial times. But not sure which one violate the
guide?

@Bjorn Helgaas. How do you think so? 

best regards
Frank Li

> 
> > Frank
> > 
> > > 
> > > >  drivers/pci/controller/dwc/pci-layerscape.c | 88 ++++++++++++++++++++-
> > > >  1 file changed, 87 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
> > > > index 20c48c06e2248..bc5a8ff1a26ce 100644
> > > > --- a/drivers/pci/controller/dwc/pci-layerscape.c
> > > > +++ b/drivers/pci/controller/dwc/pci-layerscape.c
> > > > @@ -35,6 +35,12 @@
> > > >  #define PF_MCR_PTOMR		BIT(0)
> > > >  #define PF_MCR_EXL2S		BIT(1)
> > > >  
> > > > +/* LS1021A PEXn PM Write Control Register */
> > > > +#define SCFG_PEXPMWRCR(idx)	(0x5c + (idx) * 0x64)
> > > > +#define PMXMTTURNOFF		BIT(31)
> > > > +#define SCFG_PEXSFTRSTCR	0x190
> > > > +#define PEXSR(idx)		BIT(idx)
> > > > +
> > > >  #define PCIE_IATU_NUM		6
> > > >  
> > > >  struct ls_pcie_drvdata {
> > > > @@ -48,6 +54,8 @@ struct ls_pcie {
> > > >  	struct dw_pcie *pci;
> > > >  	const struct ls_pcie_drvdata *drvdata;
> > > >  	void __iomem *pf_base;
> > > > +	struct regmap *scfg;
> > > > +	int index;
> > > >  	bool big_endian;
> > > >  };
> > > >  
> > > > @@ -170,13 +178,91 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp)
> > > >  	return 0;
> > > >  }
> > > >  
> > > > +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
> > > > +{
> > > > +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > +	struct ls_pcie *pcie = to_ls_pcie(pci);
> > > > +	u32 val;
> > > > +
> > > > +	if (!pcie->scfg) {
> > > > +		dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n");
> > > > +		return;
> > > > +	}
> > > > +
> > > > +	/* Send Turn_off message */
> > > > +	regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val);
> > > > +	val |= PMXMTTURNOFF;
> > > > +	regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val);
> > > > +
> > > > +	/* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */
> > > > +	mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000);
> > > > +
> > > > +	/* Clear Turn_off message */
> > > > +	regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val);
> > > > +	val &= ~PMXMTTURNOFF;
> > > > +	regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val);
> > > > +}
> > > > +
> > > > +static void ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
> > > > +{
> > > > +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > +	struct ls_pcie *pcie = to_ls_pcie(pci);
> > > > +	u32 val;
> > > > +
> > > > +	regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val);
> > > > +	val |= PEXSR(pcie->index);
> > > > +	regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val);
> > > > +
> > > > +	regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val);
> > > > +	val &= ~PEXSR(pcie->index);
> > > > +	regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val);
> > > > +}
> > > > +
> > > > +static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp)
> > > > +{
> > > > +	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > +	struct ls_pcie *pcie = to_ls_pcie(pci);
> > > > +	struct device *dev = pcie->pci->dev;
> > > > +	u32 index[2];
> > > > +	int ret;
> > > > +
> > > > +	ret = ls_pcie_host_init(pp);
> > > > +	if (ret)
> > > > +		return ret;
> > > > +
> > > > +	pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg");
> > > > +	if (IS_ERR(pcie->scfg)) {
> > > > +		ret = PTR_ERR(pcie->scfg);
> > > > +		dev_err(dev, "No syscfg phandle specified\n");
> > > > +		pcie->scfg = NULL;
> > > > +		return ret;
> > > > +	}
> > > > +
> > > > +	ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2);
> > > > +	if (ret) {
> > > > +		pcie->scfg = NULL;
> > > > +		return ret;
> > > > +	}
> > > > +
> > > > +	pcie->index = index[1];
> > > > +
> > > > +	return ret;
> > > > +}
> > > > +
> > > >  static const struct dw_pcie_host_ops ls_pcie_host_ops = {
> > > >  	.host_init = ls_pcie_host_init,
> > > >  	.pme_turn_off = ls_pcie_send_turnoff_msg,
> > > >  };
> > > >  
> > > > +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = {
> > > > +	.host_init = ls1021a_pcie_host_init,
> > > > +	.pme_turn_off = ls1021a_pcie_send_turnoff_msg,
> > > > +};
> > > > +
> > > >  static const struct ls_pcie_drvdata ls1021a_drvdata = {
> > > > -	.pm_support = false,
> > > > +	.pm_support = true,
> > > > +	.ops = &ls1021a_pcie_host_ops,
> > > > +	.exit_from_l2 = ls1021a_pcie_exit_from_l2,
> > > >  };
> > > >  
> > > >  static const struct ls_pcie_drvdata layerscape_drvdata = {
> > > > -- 
> > > > 2.34.1
> > > >