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[23.128.96.37]) by mx.google.com with ESMTPS id i5-20020a170902eb4500b001c62bbdde51si3369973pli.479.2023.10.18.00.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 00:11:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 355EE806CC34; Wed, 18 Oct 2023 00:10:49 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229824AbjJRHKi (ORCPT + 99 others); Wed, 18 Oct 2023 03:10:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229657AbjJRHKe (ORCPT ); Wed, 18 Oct 2023 03:10:34 -0400 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 245FDFA for ; Wed, 18 Oct 2023 00:10:33 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qt0h1-0007Ys-S7; Wed, 18 Oct 2023 09:10:11 +0200 Received: from [2a0a:edc0:0:1101:1d::39] (helo=dude03.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1qt0gz-002V9a-3a; Wed, 18 Oct 2023 09:10:09 +0200 Received: from localhost ([::1] helo=dude03.red.stw.pengutronix.de) by dude03.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1qt0gz-003JoA-03; Wed, 18 Oct 2023 09:10:09 +0200 From: Johannes Zink Date: Wed, 18 Oct 2023 09:09:54 +0200 Subject: [PATCH net-next v2 2/5] net: stmmac: use correct PPS capture input index MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20231010-stmmac_fix_auxiliary_event_capture-v2-2-51d5f56542d7@pengutronix.de> References: <20231010-stmmac_fix_auxiliary_event_capture-v2-0-51d5f56542d7@pengutronix.de> In-Reply-To: <20231010-stmmac_fix_auxiliary_event_capture-v2-0-51d5f56542d7@pengutronix.de> To: Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Richard Cochran , Kurt Kanzenbach Cc: patchwork-jzi@pengutronix.de, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, vee.khee.wong@linux.intel.com, tee.min.tan@intel.com, rmk+kernel@armlinux.org.uk, bartosz.golaszewski@linaro.org, ahalaney@redhat.com, horms@kernel.org, Johannes Zink X-Mailer: b4 0.12.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: j.zink@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 18 Oct 2023 00:10:49 -0700 (PDT) The stmmac supports up to 4 auxiliary snapshots that can be enabled by setting the appropriate bits in the PTP_ACR bitfield. Previously as of commit f4da56529da6 ("net: stmmac: Add support for external trigger timestamping") instead of setting the bits, a fixed value was written to this bitfield instead of passing the appropriate bitmask. Now the correct bit is set according to the ptp_clock_request.extts_index passed as a parameter to stmmac_enable(). Signed-off-by: Johannes Zink --- Changelog: v1 > v2: no functional changes. reword commit message and remove fixes-tag as discussed with Simon and Jakub. Thanks to both for reviewing my patches! --- drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c | 5 ++--- drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c index f110b91af9bd..300e673d2a36 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c @@ -201,12 +201,11 @@ static int stmmac_enable(struct ptp_clock_info *ptp, acr_value &= ~PTP_ACR_MASK; if (on) { /* Enable External snapshot trigger */ - acr_value |= priv->plat->ext_snapshot_num; + acr_value |= PTP_ACR_ATSEN(rq->extts.index); acr_value |= PTP_ACR_ATSFC; } netdev_dbg(priv->dev, "Auxiliary Snapshot %d %s.\n", - priv->plat->ext_snapshot_num >> PTP_ACR_ATSEN_SHIFT, - on ? "enabled" : "disabled"); + rq->extts.index, on ? "enabled" : "disabled"); writel(acr_value, ptpaddr + PTP_ACR); mutex_unlock(&priv->aux_ts_lock); /* wait for auxts fifo clear to finish */ diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h index d1fe4b46f162..fce3fba2ffd2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h @@ -79,7 +79,7 @@ #define PTP_ACR_ATSEN1 BIT(5) /* Auxiliary Snapshot 1 Enable */ #define PTP_ACR_ATSEN2 BIT(6) /* Auxiliary Snapshot 2 Enable */ #define PTP_ACR_ATSEN3 BIT(7) /* Auxiliary Snapshot 3 Enable */ -#define PTP_ACR_ATSEN_SHIFT 5 /* Auxiliary Snapshot shift */ +#define PTP_ACR_ATSEN(index) (PTP_ACR_ATSEN0 << (index)) #define PTP_ACR_MASK GENMASK(7, 4) /* Aux Snapshot Mask */ #define PMC_ART_VALUE0 0x01 /* PMC_ART[15:0] timer value */ #define PMC_ART_VALUE1 0x02 /* PMC_ART[31:16] timer value */ -- 2.39.2