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Message-ID: <8bc65c14-7ac1-7d1f-c201-468956c560ff@quicinc.com>
Date:   Wed, 18 Oct 2023 16:26:51 +0530
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Subject: Re: [PATCH V2 2/4] clk: qcom: branch: Add mem ops support for branch2
 clocks
Content-Language: en-US
To:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
CC:     Taniya Das <quic_tdas@quicinc.com>,
        <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        Ajit Pandey <quic_ajipan@quicinc.com>,
        Jagadeesh Kona <quic_jkona@quicinc.com>
References: <20231011090028.1706653-1-quic_imrashai@quicinc.com>
 <20231011090028.1706653-3-quic_imrashai@quicinc.com>
 <ac3fc5fd-b6fa-4386-aa62-f182547d1a59@linaro.org>
From:   Imran Shaik <quic_imrashai@quicinc.com>
In-Reply-To: <ac3fc5fd-b6fa-4386-aa62-f182547d1a59@linaro.org>
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Precedence: bulk


On 10/11/2023 3:21 PM, Konrad Dybcio wrote:
> 
> 
> On 10/11/23 11:00, Imran Shaik wrote:
>> From: Taniya Das <quic_tdas@quicinc.com>
>>
>> Clock CBCRs with memories need an update for memory before enable/disable
>> of the clock, which helps retain the respective block's register 
>> contents.
>> Add support for the mem ops to handle this sequence.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
>> ---
>>   drivers/clk/qcom/clk-branch.c | 37 +++++++++++++++++++++++++++++++++++
>>   drivers/clk/qcom/clk-branch.h | 21 ++++++++++++++++++++
>>   2 files changed, 58 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/clk-branch.c 
>> b/drivers/clk/qcom/clk-branch.c
>> index fc4735f74f0f..9ac8d04b425a 100644
>> --- a/drivers/clk/qcom/clk-branch.c
>> +++ b/drivers/clk/qcom/clk-branch.c
>> @@ -1,6 +1,7 @@
>>   // SPDX-License-Identifier: GPL-2.0
>>   /*
>>    * Copyright (c) 2013, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights 
>> reserved.
>>    */
>>   #include <linux/kernel.h>
>> @@ -134,6 +135,42 @@ static void clk_branch2_disable(struct clk_hw *hw)
>>       clk_branch_toggle(hw, false, clk_branch2_check_halt);
>>   }
>> +static int clk_branch2_mem_enable(struct clk_hw *hw)
>> +{
>> +    struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
>> +    const char *name = clk_hw_get_name(&mem_br->branch.clkr.hw);
>> +    u32 val;
>> +    int timeout = 200, ret;
> Reverse-Christmas-tree, please
> 
> You can drop the timeout variable and pass the int literal.
> 

Sure, will take care of this in the next series.

>> +
>> +    regmap_update_bits(mem_br->branch.clkr.regmap, 
>> mem_br->mem_enable_reg,
>> +            mem_br->mem_enable_ack_bit, mem_br->mem_enable_ack_bit);
> This is a mask, not a bit.
> 

Yes, will check and update.

>> +
>> +    ret = regmap_read_poll_timeout(mem_br->branch.clkr.regmap, 
>> mem_br->mem_ack_reg,
>> +            val, val & mem_br->mem_enable_ack_bit, 0, timeout);
> 
> [...]
> 
>> +/**
>> + * struct clk_mem_branch - gating clock which are associated with 
>> memories
>> + *
>> + * @mem_enable_reg: branch clock memory gating register
>> + * @mem_ack_reg: branch clock memory ack register
>> + * @mem_enable_ack_bit: ANDed with @mem_ack_reg to check memory 
>> enablement
> @dog: woofs
> 
> Describe what it is instead.
> 
> Konrad

Sure, will update the description in the next series.

Thanks,
Imran