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Message-ID: <ee431c51-1474-47f9-b298-8ca284ea353b@quicinc.com>
Date:   Wed, 18 Oct 2023 19:38:44 +0530
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Subject: Re: [PATCH v2 00/11] Add GPLL0 as clock provider for the Qualcomm's
 IPQ mailbox controller
Content-Language: en-US
To:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        "Sricharan Ramabadhran" <quic_srichara@quicinc.com>,
        Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>,
        Varadarajan Narayanan <quic_varada@quicinc.com>,
        Anusha Rao <quic_anusha@quicinc.com>,
        Devi Priya <quic_devipriy@quicinc.com>,
        Jassi Brar <jassisinghbrar@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
CC:     <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <stable@vger.kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Robert Marko <robimarko@gmail.com>
References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com>
From:   Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com>
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On 9/14/2023 12:29 PM, Kathiravan Thirumoorthy wrote:
> Currently mailbox controller takes the XO and APSS PLL as the input. It
> can take the GPLL0 also as an input. This patch series adds the same and
> fixes the issue caused by this.
>
> Once the cpufreq driver is up, it tries to bump up the cpu frequency
> above 800MHz, while doing so system is going to unusable state. Reason
> being, with the GPLL0 included as clock source, clock framework tries to
> achieve the required rate with the possible parent and since GPLL0
> carries the CLK_SET_RATE_PARENT flag, clock rate of the GPLL0 is getting
> changed, causing the issue.
>
> First half of the series, removes the CLK_SET_RATE_PARENT flag from the
> PLL clocks since the PLL clock rates shouldn't be changed. Another
> half, add the necessary support to include the GPLL0 as clock provider
> for mailbox and accomodate the changes in APSS clock driver.
>
> This is also the preparatory series to enable the CPUFreq on IPQ5332
> SoC. Dynamic scaling of CPUFreq is not supported on IPQ5332, so to
> switch between the frequencies we need to park the APSS PLL in safe
> source, here it is GPLL0 and then shutdown and bring up the APSS PLL in
> the desired rate.
>
> For IPQ5332 SoC, this series depends on the below patch
> https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/


Bjorn, can this series picked up for v6.7?

There is a minor nit the commit message. The statement "APSS PLL will be 
running at 800MHz" should be "APSS clock / CPU clock will be running at 
800MHz" and this should be taken care for clk and the dts patches. Do 
let me know if I need to re-spin the address to address this.

Thanks,


>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
> Changes in v2:
> - included the patch to drop the CLK_SET_RATE_PARENT from IPQ5018 GCC driver
> - Splitted the DTS changes per target
> - For IPQ8074 and IPQ6018 keep the CLK_SET_RATE_PARENT for UBI32 PLL
>    since the PLL clock rates can be changed
> - Pick up the tags in the relevant patches
> - Link to v1: https://lore.kernel.org/r/20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com
>
> ---
> Kathiravan Thirumoorthy (11):
>        clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
>        clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
>        clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
>        clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
>        clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
>        dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox
>        clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
>        arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox
>        arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailbox
>        arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox
>        arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox
>
>   .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml          | 2 ++
>   arch/arm64/boot/dts/qcom/ipq5332.dtsi                               | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi                               | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq8074.dtsi                               | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq9574.dtsi                               | 4 ++--
>   drivers/clk/qcom/apss-ipq6018.c                                     | 3 +++
>   drivers/clk/qcom/gcc-ipq5018.c                                      | 3 ---
>   drivers/clk/qcom/gcc-ipq5332.c                                      | 2 --
>   drivers/clk/qcom/gcc-ipq6018.c                                      | 6 ------
>   drivers/clk/qcom/gcc-ipq8074.c                                      | 6 ------
>   drivers/clk/qcom/gcc-ipq9574.c                                      | 4 ----
>   11 files changed, 13 insertions(+), 29 deletions(-)
> ---
> base-commit: e143016b56ecb0fcda5bb6026b0a25fe55274f56
> change-id: 20230913-gpll_cleanup-5d0a339ebd17
>
> Best regards,