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[209.85.208.53]) by smtp.gmail.com with ESMTPSA id s23-20020a50d497000000b0053dfd3519f4sm3420566edi.22.2023.10.18.14.11.12 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Oct 2023 14:11:12 -0700 (PDT) Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-53da72739c3so12066329a12.3 for ; Wed, 18 Oct 2023 14:11:12 -0700 (PDT) X-Received: by 2002:a17:907:e94:b0:9c2:4d0a:c568 with SMTP id ho20-20020a1709070e9400b009c24d0ac568mr315639ejc.64.1697663471724; Wed, 18 Oct 2023 14:11:11 -0700 (PDT) MIME-Version: 1.0 References: <20231010164234.140750-1-ubizjak@gmail.com> <0617BB2F-D08F-410F-A6EE-4135BB03863C@vmware.com> <7D77A452-E61E-4B8B-B49C-949E1C8E257C@vmware.com> <9F926586-20D9-4979-AB7A-71124BBAABD3@vmware.com> <3F9D776E-AD7E-4814-9E3C-508550AD9287@vmware.com> <28B9471C-4FB0-4AB0-81DD-4885C3645E95@vmware.com> In-Reply-To: From: Linus Torvalds Date: Wed, 18 Oct 2023 14:10:53 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 -tip] x86/percpu: Use C for arch_raw_cpu_ptr() To: Uros Bizjak Cc: Nadav Amit , "the arch/x86 maintainers" , Linux Kernel Mailing List , Andy Lutomirski , Brian Gerst , Denys Vlasenko , "H . Peter Anvin" , Peter Zijlstra , Thomas Gleixner , Josh Poimboeuf , Nick Desaulniers Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 18 Oct 2023 14:13:33 -0700 (PDT) On Wed, 18 Oct 2023 at 13:52, Uros Bizjak wrote: > > FYI: This is the reason RMW instructions in percpu.h are not (blindly) > converted to C ops. They will remain in their (volatile or not) asm > form because of the above reason, and due to the fact that they don't > combine with anything. Well, also because converting them to C would be HORRIBYL BUGGY. They absolutely have to be a single instruction. We have architectures that can't do rmw instructions, and then they have to do lots of extra horrid crud (disable interrupts or whatever) to make a percpu 'add' be a valid thing. > Actually, RMW insns are better written in asm, while simple "mov" > should be converted to (volatile or not) memory access. No. This remat issue has convinced me that the *only* thing that should be converted to a memory access is the "stable" case (which in practice is mainly just 'current'). Because if you make them 'volatile' memory instructions, then the simple "mov" inline asm is simply better. It still allows CSE on the asm (in the "raw" form). And if you make them memory instructions _without_ the 'volatile', the memory access is simply buggy until we have some 'nomaterialize' model. So the *only* situation where a memory access is better is that 'stable' case. In all other cases they are the same or strictly worse than 'asm'. Linus