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[2620:137:e000::3:6]) by mx.google.com with ESMTPS id h8-20020a170902ac8800b001c3e8a6748asi1663436plr.644.2023.10.19.02.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 02:08:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=dhYwrGhV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id B45558198004; Thu, 19 Oct 2023 02:07:58 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232876AbjJSJHu (ORCPT + 99 others); Thu, 19 Oct 2023 05:07:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231792AbjJSJHt (ORCPT ); Thu, 19 Oct 2023 05:07:49 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44DED10F; Thu, 19 Oct 2023 02:07:47 -0700 (PDT) Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id EAE766607322; Thu, 19 Oct 2023 10:07:44 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697706466; bh=QnC5hEp1lC2GAFWQ8NBrZuVLax5LzwUML2S5Y2ebPzU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=dhYwrGhVa49q+x2y7O6/WqCi+lCfkbvHzalce+0jnzS+8pCHY64GO7l4cuiUBtJ4C xXGqci8TAzSfkPLUitpqNvDWh+ePrCJHwSB0ZwXIpmYCjQD8RIefmaTfYCOtydrMYa Bb1ICnFLpbl2rdUKC3t0li8YbUBKNuPRIOpql15OV8nWN/IHIyChwhgGAB887PAdHL inAKT7s5b22FYRH7NPa7ZfI5Eml4e4rn6e7VfkFFjGlMrzp49+SZXp055Nd/vM+iqL jIKo2wQCejoBAzpVk32mZlwgri4wGkws8rtI77jlygOANl6fbKxeuvy879PL8OM3jR Gp6RdDJairX6A== Message-ID: <5a059ca0-fcb7-4730-a0d8-29103fb71d54@collabora.com> Date: Thu, 19 Oct 2023 11:07:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 15/24] drm/mediatek: Remove ineffectual power management codes Content-Language: en-US To: Hsiao Chien Sung , CK Hu , Krzysztof Kozlowski , Matthias Brugger , Rob Herring Cc: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Fei Shao , Sean Paul , Johnson Wang , "Nancy . Lin" , Moudy Ho , "Jason-JH . Lin" , Nathan Lu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org References: <20231019055619.19358-1-shawn.sung@mediatek.com> <20231019055619.19358-16-shawn.sung@mediatek.com> From: AngeloGioacchino Del Regno In-Reply-To: <20231019055619.19358-16-shawn.sung@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=1.4 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,TVD_SUBJ_WIPE_DEBT autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 19 Oct 2023 02:07:59 -0700 (PDT) X-Spam-Level: * Il 19/10/23 07:56, Hsiao Chien Sung ha scritto: > Display modules will be powered on when .atomic_enable(), > there is no need to do it again in mtk_crtc_ddp_hw_init(). > Besides, the DRM devices are created manually when mtk-mmsys > is probed and there is no power domain linked to it. > > Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.") > > Signed-off-by: Hsiao Chien Sung > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++--------------- > 1 file changed, 3 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index bc4cc75cca18..c7edd80be428 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -6,7 +6,6 @@ > #include > #include > #include > -#include > #include > #include > #include > @@ -362,22 +361,16 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc, struct drm_atomic > drm_connector_list_iter_end(&conn_iter); > } > > - ret = pm_runtime_resume_and_get(crtc->dev->dev); > - if (ret < 0) { > - DRM_ERROR("Failed to enable power domain: %d\n", ret); > - return ret; > - } > - Are you really sure that writes to DISP_REG_OVL_xxx and others in other modules, called by the .layer_config() callback, can be successfully done on an unpowered and/or unclocked module, on all MediaTek SoCs? This looks a bit odd. > ret = mtk_mutex_prepare(mtk_crtc->mutex); > if (ret < 0) { > DRM_ERROR("Failed to enable mutex clock: %d\n", ret); > - goto err_pm_runtime_put; > + goto error; > } > > ret = mtk_crtc_ddp_clk_enable(mtk_crtc); > if (ret < 0) { > DRM_ERROR("Failed to enable component clocks: %d\n", ret); > - goto err_mutex_unprepare; > + goto error; > } > > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { > @@ -426,16 +419,13 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc, struct drm_atomic > ...because you could otherwise just call pm_runtime_put() here, instead of removing the pm_runtime_resume_and_get() call, which is something I would advise to do. Regards, Angelo > return 0; > > -err_mutex_unprepare: > +error: > mtk_mutex_unprepare(mtk_crtc->mutex); > -err_pm_runtime_put: > - pm_runtime_put(crtc->dev->dev); > return ret; > } > > static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) > { > - struct drm_device *drm = mtk_crtc->base.dev; > struct drm_crtc *crtc = &mtk_crtc->base; > int i; > > @@ -465,8 +455,6 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) > mtk_crtc_ddp_clk_disable(mtk_crtc); > mtk_mutex_unprepare(mtk_crtc->mutex); > > - pm_runtime_put(drm->dev); > - > if (crtc->state->event && !crtc->state->active) { > spin_lock_irq(&crtc->dev->event_lock); > drm_crtc_send_vblank_event(crtc, crtc->state->event);