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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id e7-20020a195007000000b0050574829e48sm1075529lfb.298.2023.10.19.04.22.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Oct 2023 04:22:36 -0700 (PDT) Message-ID: <76b652c8-041c-49d6-9804-2781fe2ccfe3@linaro.org> Date: Thu, 19 Oct 2023 13:22:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/11] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks Content-Language: en-US To: Stephen Boyd , Andy Gross , Anusha Rao , Bjorn Andersson , Conor Dooley , Devi Priya , Gokul Sriram Palanisamy , Jassi Brar , Kathiravan Thirumoorthy , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Sricharan Ramabadhran , Varadarajan Narayanan Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, stable@vger.kernel.org References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> <20230913-gpll_cleanup-v2-1-c8ceb1a37680@quicinc.com> <76f3bc23-8677-42bd-a3a5-43b17cbe552e@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 19 Oct 2023 04:22:49 -0700 (PDT) On 10/19/23 02:16, Stephen Boyd wrote: > Quoting Konrad Dybcio (2023-09-15 05:19:56) >> On 14.09.2023 08:59, Kathiravan Thirumoorthy wrote: >>> GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based >>> on the request from dependent clocks. Doing so will result in the >>> unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL >>> clocks. >>> >>> Cc: stable@vger.kernel.org >>> Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") >>> Signed-off-by: Kathiravan Thirumoorthy >>> --- >> Stephen, do you think there should be some sort of error >> or at least warning thrown when SET_RATE_PARENT is used with >> RO ops? >> > > Sure? How would that be implemented? drivers/clk/clk.c : static void clk_change_rate() if (!skip_set_rate && core->ops->set_rate) core->ops->set_rate(core->hw, core->new_rate, best_parent_rate); -> if (!skip_set_rate) { if (core->ops->set_rate) core->ops->set_rate(core->hw, core->new_rate, best_parent_rate); else pr_err("bad idea"); } Konrad