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Date:   Thu, 19 Oct 2023 20:02:16 +0800
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v4 5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
To:     Inochi Amaoto <inochiama@outlook.com>,
        Chao Wei <chao.wei@sophgo.com>,
        Conor Dooley <conor@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>
Cc:     Jisheng Zhang <jszhang@kernel.org>,
        linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
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From:   Chen Wang <unicorn_wang@outlook.com>
In-Reply-To: <IA1PR20MB4953C1E5F9EAA3699EA1D3DDBBD5A@IA1PR20MB4953.namprd20.prod.outlook.com>
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On 2023/10/19 7:18, Inochi Amaoto wrote:
> Add common GPIO devices for the CV180x and CV181x soc.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>

LGTM.

Acked-by: Chen Wang <unicorn_wang@outlook.com>

> ---
>   arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 73 ++++++++++++++++++++++++++
>   1 file changed, 73 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 55d4bc84faa0..d415cc758def 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -1,6 +1,7 @@
>   // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>   /*
>    * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
>    */
>
>   #include <dt-bindings/interrupt-controller/irq.h>
> @@ -53,6 +54,78 @@ soc {
>   		dma-noncoherent;
>   		ranges;
>
> +		gpio0: gpio@3020000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x3020000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			porta: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		gpio1: gpio@3021000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x3021000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			portb: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		gpio2: gpio@3022000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x3022000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			portc: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
> +		gpio3: gpio@3023000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x3023000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			portd: gpio-controller@0 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				ngpios = <32>;
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +
>   		uart0: serial@4140000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x04140000 0x100>;
> --
> 2.42.0
>