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From:   Adam Ford <aford173@gmail.com>
Date:   Thu, 19 Oct 2023 07:32:04 -0500
Message-ID: <CAHCN7xLbpbaCa2M7dQfkr1jTGKwn_qmQzRRKB1RfBE5_N7nSzQ@mail.gmail.com>
Subject: Re: [PATCH] arm64: dts: imx8mp: Add NPU Node
To:     Alexander Stein <alexander.stein@ew.tq-group.com>
Cc:     linux-arm-kernel@lists.infradead.org, l.stach@pengutronix.de,
        aford@beaconembedded.com, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
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On Thu, Oct 19, 2023 at 1:00=E2=80=AFAM Alexander Stein
<alexander.stein@ew.tq-group.com> wrote:
>
> Hi Adam,
>
> thanks for the patch I tried a similar one.
>
> Am Donnerstag, 19. Oktober 2023, 04:23:00 CEST schrieb Adam Ford:
> > The NPU is based on the Vivante GC8000 and it enumerates as
> >
> >  etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> > c9a610ba4836..1ef8d17726ac 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -2012,6 +2012,25 @@ vpumix_blk_ctrl: blk-ctrl@38330000 {
> >                       interconnect-names =3D "g1", "g2", "vc8000e";
> >               };
> >
> > +             npu: npu@38500000 {
> > +                     compatible =3D "vivante,gc";
> > +                     reg =3D <0x38500000 0x20000>;
>
> Do you have some more information about the actual memory range? RM says =
2MiB,
> but NPU memory map lists up to 0x664.

I do not. The RM lists 3850_0000 - 386F_FFFF, so I should have put an
extra 0 in there.  Sorry about that.  I will fix in the next rev.
>
> > +                     interrupts =3D <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks =3D <&clk IMX8MP_CLK_NPU_ROOT>,
> > +                              <&clk IMX8MP_CLK_NPU_ROOT>,
> > +                              <&clk IMX8MP_CLK_ML_AXI>,
> > +                              <&clk IMX8MP_CLK_ML_AHB>;
> > +                     clock-names =3D "core", "shader", "bus", "reg";
> > +                     assigned-clocks =3D <&clk IMX8MP_CLK_ML_CORE>,
> > +                               <&clk IMX8MP_CLK_ML_AXI>,
> > +                               <&clk IMX8MP_CLK_ML_AHB>;
> > +                     assigned-clock-parents =3D <&clk
> IMX8MP_SYS_PLL2_1000M>,
> > +                                      <&clk
> IMX8MP_SYS_PLL1_800M>,
> > +                                      <&clk
> IMX8MP_SYS_PLL1_800M>;
> > +                     assigned-clock-rates =3D <1000000000>,
> <800000000>, <400000000>;
>
> 1GHz for ML_CLK_ROOT is only available in overdrive mode, 800MHz in nomin=
al
> mode. See datasheet IMX8MPIEC Rev 2.1. I don't think it's a good idea to
> configure for overdrive mode by default.

You are right.  I looked at the clocking from the downstream tree to
see what their clocks were, and it didn't occur to me to double check
against the datasheet.

> Same goes for CLK_ML_AHB regarding 400 vs. 300 MHz.

I'll update both and submit  a V2.

adam
>
> Best regards,
> Alexander
>
> > +                     power-domains =3D <&pgc_mlmix>;
> > +             };
> > +
> >               gic: interrupt-controller@38800000 {
> >                       compatible =3D "arm,gic-v3";
> >                       reg =3D <0x38800000 0x10000>,
>
>
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