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Message-ID: <45a14ebb-91e7-489d-ad5d-6d39a48bc1f5@linux.vnet.ibm.com>
Date:   Thu, 19 Oct 2023 21:26:56 +0530
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Subject: Re: [PATCH v2 2/6] powerpc/smp: Enable Asym packing for cores on
 shared processor
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To:     Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc:     Mark Rutland <mark.rutland@arm.com>,
        Valentin Schneider <vschneid@redhat.com>,
        Peter Zijlstra <peterz@infradead.org>,
        linux-kernel@vger.kernel.org, Rohan McLure <rmclure@linux.ibm.com>,
        Nicholas Piggin <npiggin@gmail.com>,
        linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
        Josh Poimboeuf <jpoimboe@kernel.org>,
        Michael Ellerman <mpe@ellerman.id.au>
References: <20231018163751.2423181-1-srikar@linux.vnet.ibm.com>
 <20231018163751.2423181-3-srikar@linux.vnet.ibm.com>
From:   Shrikanth Hegde <sshegde@linux.vnet.ibm.com>
In-Reply-To: <20231018163751.2423181-3-srikar@linux.vnet.ibm.com>
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On 10/18/23 10:07 PM, Srikar Dronamraju wrote:
> If there are shared processor LPARs, underlying Hypervisor can have more
> virtual cores to handle than actual physical cores.
> 
> Starting with Power 9, a core has 2 nearly independent thread groups.
> On a shared processors LPARs, it helps to pack threads to lesser number
> of cores so that the overall system performance and utilization
> improves. PowerVM schedules at a core level. Hence packing to fewer
> cores helps.
> 
> For example: Lets says there are two 8-core Shared LPARs that are
> actually sharing a 8 Core shared physical pool, each running 8 threads
> each. Then Consolidating 8 threads to 4 cores on each LPAR would help
> them to perform better. This is because each of the LPAR will get
> 100% time to run applications and there will no switching required by
> the Hypervisor.
> 
> To achieve this, enable SD_ASYM_PACKING flag at CACHE, MC and DIE level.

This would have a conflict with tip/master. 
DIE has been renamed to PKG and Both changelog and code below should 
change DIE to PKG. 

> 
> Signed-off-by: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
> ---
> Changelog:
> v1->v2: Using static key instead of a variable.
> 
>  arch/powerpc/kernel/smp.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> index 37c41297c9ce..498c2d51fc20 100644
> --- a/arch/powerpc/kernel/smp.c
> +++ b/arch/powerpc/kernel/smp.c
> @@ -1009,9 +1009,20 @@ static int powerpc_smt_flags(void)
>   */
>  static int powerpc_shared_cache_flags(void)
>  {
> +	if (static_branch_unlikely(&powerpc_asym_packing))
> +		return SD_SHARE_PKG_RESOURCES | SD_ASYM_PACKING;
> +
>  	return SD_SHARE_PKG_RESOURCES;
>  }
> 
> +static int powerpc_shared_proc_flags(void)
> +{
> +	if (static_branch_unlikely(&powerpc_asym_packing))
> +		return SD_ASYM_PACKING;
> +
> +	return 0;
> +}
> +
>  /*
>   * We can't just pass cpu_l2_cache_mask() directly because
>   * returns a non-const pointer and the compiler barfs on that.
> @@ -1048,8 +1059,8 @@ static struct sched_domain_topology_level powerpc_topology[] = {
>  	{ cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
>  #endif
>  	{ shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) },
> -	{ cpu_mc_mask, SD_INIT_NAME(MC) },
> -	{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
> +	{ cpu_mc_mask, powerpc_shared_proc_flags, SD_INIT_NAME(MC) },
> +	{ cpu_cpu_mask, powerpc_shared_proc_flags, SD_INIT_NAME(DIE) },
>  	{ NULL, },
>  };
> 
> @@ -1687,6 +1698,8 @@ static void __init fixup_topology(void)
>  	if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
>  		pr_info_once("Enabling Asymmetric SMT scheduling\n");
>  		static_branch_enable(&powerpc_asym_packing);
> +	} else if (is_shared_processor() && has_big_cores) {
> +		static_branch_enable(&powerpc_asym_packing);
>  	}
> 
>  #ifdef CONFIG_SCHED_SMT