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From:   "Havalige, Thippeswamy" <thippeswamy.havalige@amd.com>
To:     "Havalige, Thippeswamy" <thippeswamy.havalige@amd.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
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        <linux-arm-kernel@lists.infradead.org>
CC:     "bhelgaas@google.com" <bhelgaas@google.com>,
        "lpieralisi@kernel.org" <lpieralisi@kernel.org>,
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        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "colnor+dt@kernel.org" <colnor+dt@kernel.org>,
        "Simek, Michal" <michal.simek@amd.com>,
        "Gogada, Bharat Kumar" <bharat.kumar.gogada@amd.com>
Subject: RE: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256
 buses during
Thread-Topic: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256
 buses during
Thread-Index: AQHZ/+89QXgcS12G7EKSCK4TL1ydHbBSgl0g
Date:   Fri, 20 Oct 2023 10:35:46 +0000
Message-ID: <SN7PR12MB7201A57631FB1E0FB60A9BC08BDBA@SN7PR12MB7201.namprd12.prod.outlook.com>
References: <20231016051102.1180432-1-thippeswamy.havalige@amd.com>
In-Reply-To: <20231016051102.1180432-1-thippeswamy.havalige@amd.com>
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Hi Bjorn,

Can you please provide an update on this patch series.

Regards,
Thippeswamy H

> -----Original Message-----
> From: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> Sent: Monday, October 16, 2023 10:41 AM
> To: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com;
> robh@kernel.org; krzysztof.kozlowski+dt@linaro.org; colnor+dt@kernel.org;
> Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; Simek, Michal
> <michal.simek@amd.com>; Gogada, Bharat Kumar
> <bharat.kumar.gogada@amd.com>
> Subject: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256
> buses during
>=20
> Current driver is supports up to 16 buses. The following code fixes to su=
pport
> up to 256 buses.
>=20
> update "NWL_ECAM_VALUE_DEFAULT " to 16  can access up to 256MB ECAM
> region to detect 256 buses.
>=20
> Update ecam size to 256MB in device tree binding example.
>=20
> Remove unwanted code.
>=20
> Thippeswamy Havalige (4):
>   PCI: xilinx-nwl: Remove unnecessary code which updates primary,
>     secondary and sub-ordinate bus numbers
>   dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
>   PCI: xilinx-nwl: Rename ECAM size default macro
>   PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
>=20
>  .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml |  2 +-
>  drivers/pci/controller/pcie-xilinx-nwl.c       | 18 +++---------------
>  2 files changed, 4 insertions(+), 16 deletions(-)
>=20
> --
> 2.25.1