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[23.128.96.35]) by mx.google.com with ESMTPS id mq15-20020a17090b380f00b0027d2db562d2si3022349pjb.161.2023.10.20.18.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 18:29:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BNXqtnlD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 2972E83383F0; Fri, 20 Oct 2023 18:29:11 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232887AbjJUB21 (ORCPT + 99 others); Fri, 20 Oct 2023 21:28:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229500AbjJUB2Z (ORCPT ); Fri, 20 Oct 2023 21:28:25 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24622D68; Fri, 20 Oct 2023 18:28:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697851704; x=1729387704; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=mUdZYVXimImfRLdgMfRGzWaY3JrjlP3m7bhFqgBKk8k=; b=BNXqtnlDZAOoc4pm/ZziKCBLkJ1HK8gnKNgcmCMio+Uqx9WCEqqSOrcx Qm2WXm3tmsPKL9TtpW4Ez004xS+9sC599Wn6cBtDdA6I5l3XQ4xIhJFYl VWnKrdkZ+S6qdgqKHxoVxDvnTETtPTg0ZsRjT2gsyqAi+VMmFhEFT/cl7 AjJcQxXrGkGfI+nxlD11MvY9W28ZvG16Jc8OhrO69cHV9coT+ci887Wuz vgqWGF7cYfwtH7LnSJoG06gk/31xPNqmLQFqzsqw0p3XYPDC/ZaVtOSlp Y4o6dct2r4nNFW2eGB8BsfEmpiwVcpcJHGQt5Rx3x1oIZdcafpeo6AYsm Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10869"; a="389453049" X-IronPort-AV: E=Sophos;i="6.03,239,1694761200"; d="scan'208";a="389453049" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2023 18:28:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10869"; a="823428780" X-IronPort-AV: E=Sophos;i="6.03,239,1694761200"; d="scan'208";a="823428780" Received: from hkchanda-mobl.amr.corp.intel.com (HELO desk) ([10.209.90.113]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2023 18:28:22 -0700 Date: Fri, 20 Oct 2023 18:28:11 -0700 From: Pawan Gupta To: Andi Kleen Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Josh Poimboeuf , Andy Lutomirski , Jonathan Corbet , Sean Christopherson , Paolo Bonzini , tony.luck@intel.com, tim.c.chen@linux.intel.com, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, Alyssa Milburn , Daniel Sneddon , antonio.gomez.iglesias@linux.intel.com Subject: Re: [PATCH 3/6] x86/entry_32: Add VERW just before userspace transition Message-ID: <20231021012744.3yz7lpo2w6gyvytr@desk> References: <20231020-delay-verw-v1-0-cff54096326d@linux.intel.com> <20231020-delay-verw-v1-3-cff54096326d@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Fri, 20 Oct 2023 18:29:11 -0700 (PDT) On Fri, Oct 20, 2023 at 04:49:34PM -0700, Andi Kleen wrote: > On Fri, Oct 20, 2023 at 01:45:09PM -0700, Pawan Gupta wrote: > > As done for entry_64, add support for executing VERW late in exit to > > user path for 32-bit mode. > > > > Signed-off-by: Pawan Gupta > > --- > > arch/x86/entry/entry_32.S | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S > > index 6e6af42e044a..bbf77d2aab2e 100644 > > --- a/arch/x86/entry/entry_32.S > > +++ b/arch/x86/entry/entry_32.S > > @@ -886,6 +886,9 @@ SYM_FUNC_START(entry_SYSENTER_32) > > popfl > > popl %eax > > > > + /* Mitigate CPU data sampling attacks .e.g. MDS */ > > + USER_CLEAR_CPU_BUFFERS > > + > > /* > > * Return back to the vDSO, which will pop ecx and edx. > > * Don't bother with DS and ES (they already contain __USER_DS). > > Did you forget the INT 0x80 entry point? I do have VERW in the INT80 path, the diff is showing just the label restore_all_switch_stack. Below is the sequence: SYM_FUNC_START(entry_INT80_32) ASM_CLAC pushl %eax /* pt_regs->orig_ax */ SAVE_ALL pt_regs_ax=$-ENOSYS switch_stacks=1 /* save rest */ movl %esp, %eax call do_int80_syscall_32 .Lsyscall_32_done: STACKLEAK_ERASE restore_all_switch_stack: SWITCH_TO_ENTRY_STACK CHECK_AND_APPLY_ESPFIX /* Switch back to user CR3 */ SWITCH_TO_USER_CR3 scratch_reg=%eax BUG_IF_WRONG_CR3 /* Restore user state */ RESTORE_REGS pop=4 # skip orig_eax/error_code /* Mitigate CPU data sampling attacks .e.g. MDS */ USER_CLEAR_CPU_BUFFERS ^^^^^^^^^^^^^^^^^^^^^^