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From:   Vishal Annapurve <vannapurve@google.com>
Date:   Sat, 21 Oct 2023 07:24:55 +0530
Message-ID: <CAGtprH8-jiC+wsy2LgmZimrRUT6kuntD6EJso2Mvx5Y42za9Dw@mail.gmail.com>
Subject: Re: [PATCH] x86/tdx: Override the tsc calibration for TDX VMs
To:     Sean Christopherson <seanjc@google.com>
Cc:     "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Jun Nakajima <jun.nakajima@intel.com>,
        Isaku Yamahata <isaku.yamahata@intel.com>,
        Erdem Aktas <erdemaktas@google.com>,
        Sagi Shahar <sagis@google.com>,
        Nikolay Borisov <nik.borisov@suse.com>,
        "Jason A. Donenfeld" <Jason@zx2c4.com>,
        Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@linux.intel.com>,
        "H. Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        linux-kernel@vger.kernel.org
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On Sat, Oct 14, 2023 at 4:32=E2=80=AFAM Sean Christopherson <seanjc@google.=
com> wrote:
>
> On Fri, Oct 13, 2023, Sean Christopherson wrote:
> > On Fri, Oct 06, 2023, Vishal Annapurve wrote:
> > > TSC calibration for native execution gets the TSC frequency from CPUI=
D,
> > > but also ends up setting lapic_timer_period. When using oneshot mode
> > > with lapic timer, predefined value of lapic_timer_period causes lapic
> > > timer calibration to be skipped with wrong multipliers set for lapic
> > > timer.
> > >
> > > To avoid this issue, override the TSC calibration step for TDX VMs to
> > > just calculate the TSC frequency using cpuid values.
> >
> > This is a hack to workaround a KVM TDX bug.  Per Intel's SDM:
> >
> >   The APIC timer frequency will be the processor=E2=80=99s bus clock or=
 core crystal
> >   clock frequency (when TSC/core crystal clock ratio is enumerated in C=
PUID
> >   leaf 0x15) divided by the value specified in the divide configuration=
 register.
> >
> > TDX hardcodes the core crystal frequency to 25Mhz, whereas KVM hardcode=
s the APIC
> > bus frequency to 1Ghz.  Upstream KVM's *current* behavior is fine, beca=
use KVM
> > doesn't advertise support for CPUID 0x15, i.e. doesn't announce to host=
 userspace
> > that it's safe to expose CPUID 0x15 to the guest.  Because TDX makes ex=
posing
> > CPUID 0x15 mandatory, KVM needs to be taught to correctly emulate the g=
uest's
> > APIC bus frequency, a.k.a. the TDX guest core crystal frequency of 25Mh=
z.
> >

Ack, makes sense to pursue this fix from the KVM TDX side instead of
guest changes as per your suggestion.

>
>
> > I.e. tmict_to_ns() needs to replace APIC_BUS_CYCLE_NS with some math th=
at makes
> > the guest's APIC timer actually run at 25Mhz given whatever the host AP=
IC bus
> > runs at.
> >
> >   static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)
> >   {
> >       return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count;
> >   }
>