Received: by 2002:a05:7412:251c:b0:e2:908c:2ebd with SMTP id w28csp160727rda; Sat, 21 Oct 2023 02:48:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF3XWk4y1O9zgtLjkdINzosgLLhHuqQedmtDMOPdvUYc7apkmig5k8GK/0JlfOha4OKhuaY X-Received: by 2002:a05:6870:912a:b0:1ea:7c8a:c9dc with SMTP id o42-20020a056870912a00b001ea7c8ac9dcmr4481302oae.26.1697881692322; Sat, 21 Oct 2023 02:48:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697881692; cv=none; d=google.com; s=arc-20160816; b=i7QIV0yUsMnINvEZ/zdQlRwPIt4irttlndEv30KdDHy1TJOQnqPkupS1QkD43ovMEd 4Gp71HDf0GkB5x2T+LE49oxLUi+yPGlRAgStObTjP3zxvUwC/u3vUhPuQIO1qCczZg5v P3dv0znPm26bGTUipsD4JhZqVDQiUotwY4JudD2MrfO33vN1Zrp5i2x5BJGqJYqBmTFf tmVdOi0Gw/EZmqF7oDk7z0JNVxtOrgHvFMZ+yZqbIaz/mcVN+Eeco37Jw0Y/zR/ZxSiF OC2PdoeBWFEitBh+pHTCDDePPubW3f7GdNvo24kncfhUkwKpcEhMn+da9M1V2R7W4mxS vQmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=btfsvtjeNmNFNqPdRQ33LFhEphT53dObx4LFlgsE17Y=; fh=hadP/Qit0fP83aE7jDic8vfKKSMzMzFbjuOmlm+1S4s=; b=gJugab8Kusoen9ZJCGy3ZjhtBSvGnmF7lmBYjhrq2Y6myyPjdSF7mnV/Rw3tsoPEdl OiltvJO0OJ9/zKyMbmljCTfpmlFCyXRYVPWqMbFxQAKXu2Uzf8okkdwo9vJNZrM8beGr QlTI4nA8Z68gh9aBum12VWwlpLTqZmEgWuI7W82LRNEaFSTLLUQU22OgYBEL5Z5e5y6J 4mTYJhmiErCwc7xFzfN5o9d9h7b/b4aXNWOC239i77TW/zE8Em5/0bcUmJ2v/o/BBvCI CAjZit0ed63q2IRuoxVhw2dWm9FRFADUrKPocpzfByOoIMTUH3v1I3Lp99hIAuMYDFZD Os6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=idEU5E+v; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Return-Path: Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id w14-20020a17090a780e00b002791bfc67bdsi3315759pjk.41.2023.10.21.02.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Oct 2023 02:48:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=idEU5E+v; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 845618022B34; Sat, 21 Oct 2023 02:48:07 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230208AbjJUJra (ORCPT + 99 others); Sat, 21 Oct 2023 05:47:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230178AbjJUJr2 (ORCPT ); Sat, 21 Oct 2023 05:47:28 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29449D7F; Sat, 21 Oct 2023 02:47:22 -0700 (PDT) Received: from localhost (89-26-75-29.dyn.cablelink.at [89.26.75.29]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sebastianfricke) by madras.collabora.co.uk (Postfix) with ESMTPSA id 707A26607314; Sat, 21 Oct 2023 10:47:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697881641; bh=MW4fq3IoOrkm/uKuin0n5jWD7y//DvYP8PEHA13Kat8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=idEU5E+v2YLIbsQ2nZiOOu6R4Lp5Q9MJblCkcY0SpRr0Pw0iYYt+uckIZz54FRPlX 7Xs6h1XkwQz7D7QsFYgX3fRGQjW8WkBgLQWcDoL0ZyCC5xKawEkJD+del6x4Fb9kDZ h3fvzXQTvReuOKngWoZVEWmZW78Zb9+Po4ach4DQpeC10OX7ukdqDiA4SKUx92Dcd2 tbJ/ZYSq/PehDv4s2DSalNdHnvxo9ViRmAs3yKl968PODM0pk+OdCz8pXiHMIuHsUf D3a+KviTUvxIGwmYz8cgX1WXyXk+dfjUDhAUtYl0dRzVgBIiaoFk7rQuXlVZvg59Ij ORPQPK6vBZNrw== Date: Sat, 21 Oct 2023 11:47:18 +0200 From: Sebastian Fricke To: Yunfei Dong Cc: =?utf-8?B?TsOtY29sYXMgRiAuIFIgLiBBIC4=?= Prado , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert , Chen-Yu Tsai , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com Subject: Re: [PATCH 3/7] media: mediatek: vcodec: Setting the supported h265 level for each platform Message-ID: <20231021094718.fgy32sevjjdx2d3c@basti-XPS-13-9310> References: <20231016064346.31451-1-yunfei.dong@mediatek.com> <20231016064346.31451-3-yunfei.dong@mediatek.com> <20231021092535.hna2fzgbevluczm4@basti-XPS-13-9310> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Disposition: inline In-Reply-To: <20231021092535.hna2fzgbevluczm4@basti-XPS-13-9310> X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Sat, 21 Oct 2023 02:48:07 -0700 (PDT) Hey Yunfei, please replace Setting with Set in the title. On 21.10.2023 11:25, Sebastian Fricke wrote: >Hey Yunfei, > >On 16.10.2023 14:43, Yunfei Dong wrote: >>The supported resolution and fps of different platforms are not the >>same. Need to set the supported level according to the chip name. > >I would suggest the following rewording: > >Set the maximum H265 codec level for each platform. >The various mediatek platforms support different levels for decoding, >the level of the codec limits among others the maximum resolution, bit >rate and frame rate for the decoder. > >With that you can add: >Reviewed-by: Sebastian Fricke > >Regards, >Sebastian > >>Signed-off-by: Yunfei Dong >>--- >>.../vcodec/decoder/mtk_vcodec_dec_stateless.c | 28 +++++++++++++++++++ >>1 file changed, 28 insertions(+) >> >>diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >>index f4af81bddc58..1fdb21dbacb8 100644 >>--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >>+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >>@@ -147,6 +147,16 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { >> }, >> .codec_type = V4L2_PIX_FMT_HEVC_SLICE, >> }, >>+ { >>+ .cfg = { >>+ .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, >>+ .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, >>+ .def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, >>+ .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, >>+ }, >>+ .codec_type = V4L2_PIX_FMT_HEVC_SLICE, >>+ }, >>+ >> { >> .cfg = { >> .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, >>@@ -549,6 +559,20 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, >> }; >>} >> >>+static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, >>+ struct mtk_vcodec_dec_ctx *ctx) >>+{ >>+ switch (ctx->dev->chip_name) { >>+ case MTK_VDEC_MT8188: >>+ case MTK_VDEC_MT8195: >>+ cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; >>+ break; >>+ default: >>+ cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4; >>+ break; >>+ }; >>+} >>+ >>static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, >> struct mtk_vcodec_dec_ctx *ctx) >>{ >>@@ -557,6 +581,10 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, >> mtk_vcodec_dec_fill_h264_level(cfg, ctx); >> mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def); >> break; >>+ case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: >>+ mtk_vcodec_dec_fill_h265_level(cfg, ctx); >>+ mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def); >>+ break; >> default: >> break; >> }; >>-- >>2.18.0 >>