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From:   "Drewek, Wojciech" <wojciech.drewek@intel.com>
To:     Jijie Shao <shaojijie@huawei.com>,
        "yisen.zhuang@huawei.com" <yisen.zhuang@huawei.com>,
        "salil.mehta@huawei.com" <salil.mehta@huawei.com>,
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        "kuba@kernel.org" <kuba@kernel.org>,
        "pabeni@redhat.com" <pabeni@redhat.com>
CC:     "shenjian15@huawei.com" <shenjian15@huawei.com>,
        "wangjie125@huawei.com" <wangjie125@huawei.com>,
        "liuyonglong@huawei.com" <liuyonglong@huawei.com>,
        "chenhao418@huawei.com" <chenhao418@huawei.com>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH net-next] net: hns3: add some link modes for hisilicon
 device
Thread-Topic: [PATCH net-next] net: hns3: add some link modes for hisilicon
 device
Thread-Index: AQHaBU9pUcvtIx+BC0eks2ud/zch3LBXDbaw
Date:   Mon, 23 Oct 2023 08:55:38 +0000
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References: <20231023010836.507078-1-shaojijie@huawei.com>
In-Reply-To: <20231023010836.507078-1-shaojijie@huawei.com>
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> -----Original Message-----
> From: Jijie Shao <shaojijie@huawei.com>
> Sent: Monday, October 23, 2023 3:09 AM
> To: yisen.zhuang@huawei.com; salil.mehta@huawei.com; davem@davemloft.net;=
 edumazet@google.com; kuba@kernel.org;
> pabeni@redhat.com
> Cc: shenjian15@huawei.com; wangjie125@huawei.com; liuyonglong@huawei.com;=
 shaojijie@huawei.com;
> chenhao418@huawei.com; netdev@vger.kernel.org; linux-kernel@vger.kernel.o=
rg
> Subject: [PATCH net-next] net: hns3: add some link modes for hisilicon de=
vice
>=20
> From: Hao Chen <chenhao418@huawei.com>
>=20
> Add HCLGE_SUPPORT_50G_R1_BIT and HCLGE_SUPPORT_100G_R2_BIT two
> capability bits and Corresponding link modes.
>=20
> Signed-off-by: Hao Chen <chenhao418@huawei.com>
> Signed-off-by: Jijie Shao <shaojijie@huawei.com>
> ---
>  .../hisilicon/hns3/hns3pf/hclge_main.c        | 162 +++++++++---------
>  .../hisilicon/hns3/hns3pf/hclge_main.h        |  16 +-
>  2 files changed, 96 insertions(+), 82 deletions(-)
>=20
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/dr=
ivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
> index c42574e29747..d5ba56854ec8 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
> @@ -881,8 +881,8 @@ static const struct hclge_speed_bit_map speed_bit_map=
[] =3D {
>  	{HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},
>  	{HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},
>  	{HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},
> -	{HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT},
> -	{HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT},
> +	{HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS},
> +	{HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS},
>  	{HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},
>  };
>=20
> @@ -939,100 +939,102 @@ static void hclge_update_fec_support(struct hclge=
_mac *mac)
>  				 mac->supported);
>  }
>=20
> +static const struct hclge_link_mode_bit_map hclge_sr_link_mode_bit_map[8=
] =3D {

Names of those arrays are a bit too long. I know this is a standard here bu=
t I'm not sure if=20
"bit_map" at the end is necessary.

> +	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT},
> +	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT},
> +	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT},
> +	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT},
> +	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT},
> +	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT},
> +	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT},
> +	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},
> +};
> +
> +static const struct hclge_link_mode_bit_map hclge_lr_link_mode_bit_map[6=
] =3D {
> +	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT},
> +	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},
> +	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT=
},
> +	{HCLGE_SUPPORT_100G_R4_BIT,
> +	 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT},
> +	{HCLGE_SUPPORT_100G_R2_BIT,
> +	 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT},
> +	{HCLGE_SUPPORT_200G_BIT,
> +	 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},
> +};
> +
> +static const struct hclge_link_mode_bit_map hclge_cr_link_mode_bit_map[8=
] =3D {
> +	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT},
> +	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT},
> +	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT},
> +	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT},
> +	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT},
> +	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT},
> +	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT},
> +	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},
> +};
> +
> +static const struct hclge_link_mode_bit_map hclge_kr_link_mode_bit_map[9=
] =3D {
> +	{HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},
> +	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},
> +	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},
> +	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT},
> +	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT},
> +	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT},
> +	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},
> +	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT},
> +	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},
> +};
> +
>  static void hclge_convert_setting_sr(u16 speed_ability,
>  				     unsigned long *link_mode)
>  {
> -	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
> -				 link_mode);
> +	int i;
> +
> +	for (i =3D 0; i < ARRAY_SIZE(hclge_sr_link_mode_bit_map); i++) {
> +		if (speed_ability & hclge_sr_link_mode_bit_map[i].support_bit)
> +			linkmode_set_bit(

Checkpatch complains about wrong wrapping (here and in the next 3 functions=
):
CHECK: Lines should not end with a '('

> +				hclge_sr_link_mode_bit_map[i].link_mode,
> +				link_mode);
> +	}
>  }
>=20
>  static void hclge_convert_setting_lr(u16 speed_ability,
>  				     unsigned long *link_mode)
>  {
> -	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> -		linkmode_set_bit(
> -			ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
> -			link_mode);
> +	int i;
> +
> +	for (i =3D 0; i < ARRAY_SIZE(hclge_lr_link_mode_bit_map); i++) {
> +		if (speed_ability & hclge_lr_link_mode_bit_map[i].support_bit)
> +			linkmode_set_bit(
> +				hclge_lr_link_mode_bit_map[i].link_mode,
> +				link_mode);
> +	}
>  }
>=20
>  static void hclge_convert_setting_cr(u16 speed_ability,
>  				     unsigned long *link_mode)
>  {
> -	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
> -				 link_mode);
> +	int i;
> +
> +	for (i =3D 0; i < ARRAY_SIZE(hclge_cr_link_mode_bit_map); i++) {
> +		if (speed_ability & hclge_cr_link_mode_bit_map[i].support_bit)
> +			linkmode_set_bit(
> +				hclge_cr_link_mode_bit_map[i].link_mode,
> +				link_mode);
> +	}
>  }
>=20
>  static void hclge_convert_setting_kr(u16 speed_ability,
>  				     unsigned long *link_mode)
>  {
> -	if (speed_ability & HCLGE_SUPPORT_1G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
> -				 link_mode);
> -	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
> -		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
> -				 link_mode);
> +	int i;
> +
> +	for (i =3D 0; i < ARRAY_SIZE(hclge_kr_link_mode_bit_map); i++) {
> +		if (speed_ability & hclge_kr_link_mode_bit_map[i].support_bit)
> +			linkmode_set_bit(
> +				hclge_kr_link_mode_bit_map[i].link_mode,
> +				link_mode);
> +	}
>  }
>=20
>  static void hclge_convert_setting_fec(struct hclge_mac *mac)
> @@ -1158,10 +1160,10 @@ static u32 hclge_get_max_speed(u16 speed_ability)
>  	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
>  		return HCLGE_MAC_SPEED_200G;
>=20
> -	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
> +	if (speed_ability & HCLGE_SUPPORT_100G_BITS)
>  		return HCLGE_MAC_SPEED_100G;
>=20
> -	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
> +	if (speed_ability & HCLGE_SUPPORT_50G_BITS)
>  		return HCLGE_MAC_SPEED_50G;
>=20
>  	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/dr=
ivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> index 7bc2049b723d..ef530b84eaa0 100644
> --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
> @@ -185,15 +185,22 @@ enum HLCGE_PORT_TYPE {
>  #define HCLGE_SUPPORT_1G_BIT		BIT(0)
>  #define HCLGE_SUPPORT_10G_BIT		BIT(1)
>  #define HCLGE_SUPPORT_25G_BIT		BIT(2)
> -#define HCLGE_SUPPORT_50G_BIT		BIT(3)
> -#define HCLGE_SUPPORT_100G_BIT		BIT(4)
> +#define HCLGE_SUPPORT_50G_R2_BIT	BIT(3)
> +#define HCLGE_SUPPORT_100G_R4_BIT	BIT(4)
>  /* to be compatible with exsit board */
>  #define HCLGE_SUPPORT_40G_BIT		BIT(5)
>  #define HCLGE_SUPPORT_100M_BIT		BIT(6)
>  #define HCLGE_SUPPORT_10M_BIT		BIT(7)
>  #define HCLGE_SUPPORT_200G_BIT		BIT(8)
> +#define HCLGE_SUPPORT_50G_R1_BIT	BIT(9)
> +#define HCLGE_SUPPORT_100G_R2_BIT	BIT(10)
> +
>  #define HCLGE_SUPPORT_GE \
>  	(HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
> +#define HCLGE_SUPPORT_50G_BITS \
> +	(HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT)
> +#define HCLGE_SUPPORT_100G_BITS \
> +	(HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT)
>=20
>  enum HCLGE_DEV_STATE {
>  	HCLGE_STATE_REINITING,
> @@ -1076,6 +1083,11 @@ struct hclge_mac_speed_map {
>  	u32 speed_fw; /* speed defined in firmware */
>  };
>=20
> +struct hclge_link_mode_bit_map {
> +	u16 support_bit;
> +	enum ethtool_link_mode_bit_indices link_mode;
> +};
> +
>  int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_p=
mc,
>  				 bool en_mc_pmc, bool en_bc_pmc);
>  int hclge_add_uc_addr_common(struct hclge_vport *vport,
> --
> 2.30.0
>=20