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Mon, 23 Oct 2023 13:42:06 +0100 Date: Mon, 23 Oct 2023 13:42:05 +0100 Message-ID: <86y1ft4ijm.wl-maz@kernel.org> From: Marc Zyngier To: Raghavendra Rao Ananta Cc: Oliver Upton , Alexandru Elisei , James Morse , Suzuki K Poulose , Paolo Bonzini , Zenghui Yu , Shaoqin Huang , Jing Zhang , Reiji Watanabe , Colton Lewis , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v8 06/13] KVM: arm64: Sanitize PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} before first run In-Reply-To: <20231020214053.2144305-7-rananta@google.com> References: <20231020214053.2144305-1-rananta@google.com> <20231020214053.2144305-7-rananta@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: rananta@google.com, oliver.upton@linux.dev, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, pbonzini@redhat.com, yuzenghui@huawei.com, shahuang@redhat.com, jingzhangos@google.com, reijiw@google.com, coltonlewis@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-Spam-Status: No, score=-1.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 23 Oct 2023 05:42:37 -0700 (PDT) On Fri, 20 Oct 2023 22:40:46 +0100, Raghavendra Rao Ananta wrote: > > For unimplemented counters, the registers PM{C,I}NTEN{SET,CLR} > and PMOVS{SET,CLR} are expected to have the corresponding bits RAZ. > Hence to ensure correct KVM's PMU emulation, mask out the bits in > these registers for these unimplemented counters before the first > vCPU run. > > Signed-off-by: Raghavendra Rao Ananta > --- > arch/arm64/kvm/arm.c | 2 +- > arch/arm64/kvm/pmu-emul.c | 11 +++++++++++ > include/kvm/arm_pmu.h | 2 ++ > 3 files changed, 14 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index e3074a9e23a8b..3c0bb80483fb1 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -857,7 +857,7 @@ static int check_vcpu_requests(struct kvm_vcpu *vcpu) > } > > if (kvm_check_request(KVM_REQ_RELOAD_PMU, vcpu)) > - kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu)); > + kvm_vcpu_handle_request_reload_pmu(vcpu); Please rename this to kvm_vcpu_reload_pmu(). That's long enough. But see below. > > if (kvm_check_request(KVM_REQ_RESYNC_PMU_EL0, vcpu)) > kvm_vcpu_pmu_restore_guest(vcpu); > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index 9e24581206c24..31e4933293b76 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -788,6 +788,17 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) > return val & mask; > } > > +void kvm_vcpu_handle_request_reload_pmu(struct kvm_vcpu *vcpu) > +{ > + u64 mask = kvm_pmu_valid_counter_mask(vcpu); > + > + kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu)); > + > + __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask; > + __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= mask; > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= mask; > +} Why is this done on a vcpu request? Why can't it be done upfront, when we're requesting the reload? Or when assigning the PMU? Or when setting PMCR_EL0? M. -- Without deviation from the norm, progress is not possible.