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Date:   Mon, 23 Oct 2023 19:33:48 +0300 (EEST)
From:   =?ISO-8859-15?Q?Ilpo_J=E4rvinen?= <ilpo.jarvinen@linux.intel.com>
To:     "David E. Box" <david.e.box@linux.intel.com>
cc:     LKML <linux-kernel@vger.kernel.org>,
        platform-driver-x86@vger.kernel.org, rajvi.jingar@linux.intel.com
Subject: Re: [PATCH V4 17/17] platform/x86/intel/pmc: Show Die C6 counter on
 Meteor Lake
In-Reply-To: <20231018231624.1044633-18-david.e.box@linux.intel.com>
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References: <20231018231624.1044633-1-david.e.box@linux.intel.com> <20231018231624.1044633-18-david.e.box@linux.intel.com>
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On Wed, 18 Oct 2023, David E. Box wrote:

> Expose the Die C6 counter on Meteor Lake.
> 
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> ---
> V4 - no change
> 
> V3 - Split PATCH V2 13. Separates implementation (previous patch)
>      from platform specific use (this patch)
> 
>  drivers/platform/x86/intel/pmc/mtl.c | 32 ++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
> index 7ceeae507f4c..38c2f946ec23 100644
> --- a/drivers/platform/x86/intel/pmc/mtl.c
> +++ b/drivers/platform/x86/intel/pmc/mtl.c
> @@ -10,12 +10,17 @@
>  
>  #include <linux/pci.h>
>  #include "core.h"
> +#include "../pmt/telemetry.h"
>  
>  /* PMC SSRAM PMT Telemetry GUIDS */
>  #define SOCP_LPM_REQ_GUID	0x2625030
>  #define IOEM_LPM_REQ_GUID	0x4357464
>  #define IOEP_LPM_REQ_GUID	0x5077612
>  
> +/* Die C6 from PUNIT telemetry */
> +#define MTL_PMT_DMU_DIE_C6_OFFSET	15
> +#define MTL_PMT_DMU_GUID		0x1A067102
> +
>  static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
>  
>  /*
> @@ -968,6 +973,32 @@ static struct pmc_info mtl_pmc_info_list[] = {
>  	{}
>  };
>  
> +static void mtl_punit_pmt_init(struct pmc_dev *pmcdev)
> +{
> +	struct telem_endpoint *ep;
> +	struct pci_dev *pcidev;
> +
> +	pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(10, 0));
> +	if (!pcidev) {
> +		dev_err(&pmcdev->pdev->dev, "PUNIT PMT device not found.\n");
> +		return;
> +	}
> +
> +	ep = pmt_telem_find_and_register_endpoint(pcidev, MTL_PMT_DMU_GUID, 0);
> +	if (IS_ERR(ep)) {
> +		dev_err(&pmcdev->pdev->dev,
> +			"pmc_core: couldn't get DMU telem endpoint, %ld\n",
> +			PTR_ERR(ep));
> +		return;
> +	}
> +
> +	pci_dev_put(pcidev);
> +	pmcdev->punit_ep = ep;
> +
> +	pmcdev->has_die_c6 = true;
> +	pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
> +}
> +
>  #define MTL_GNA_PCI_DEV	0x7e4c
>  #define MTL_IPU_PCI_DEV	0x7d19
>  #define MTL_VPU_PCI_DEV	0x7d1d
> @@ -1032,6 +1063,7 @@ int mtl_core_init(struct pmc_dev *pmcdev)
>  	}
>  
>  	pmc_core_get_low_power_modes(pmcdev);
> +	mtl_punit_pmt_init(pmcdev);
>  
>  	/* Due to a hardware limitation, the GBE LTR blocks PC10
>  	 * when a cable is attached. Tell the PMC to ignore it.

Reviewed-by: Ilpo J?rvinen <ilpo.jarvinen@linux.intel.com>

-- 
 i.

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