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Message-ID: <6000957e6d7b977919eed4b7d6fe6c303066d18c.camel@collabora.com>
Subject: Re: [PATCH v5 2/2] drm/rockchip: vop: Add NV15, NV20 and NV30
 support
From:   Christopher Obbard <chris.obbard@collabora.com>
To:     Jonas Karlman <jonas@kwiboo.se>, Heiko Stuebner <heiko@sntech.de>,
        Sandy Huang <hjc@rock-chips.com>,
        Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
        Maxime Ripard <mripard@kernel.org>,
        Thomas Zimmermann <tzimmermann@suse.de>,
        David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>
Cc:     dri-devel@lists.freedesktop.org,
        linux-rockchip@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        kernel <kernel@collabora.com>
Date:   Mon, 23 Oct 2023 18:55:10 +0100
In-Reply-To: <20231023173718.188102-3-jonas@kwiboo.se>
References: <20231023173718.188102-1-jonas@kwiboo.se>
         <20231023173718.188102-3-jonas@kwiboo.se>
Autocrypt: addr=chris.obbard@collabora.com; prefer-encrypt=mutual;
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Hi Jonas,

On Mon, 2023-10-23 at 17:37 +0000, Jonas Karlman wrote:
> Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by
> the Rockchip Video Decoder on RK322X, RK3288, RK3328 and RK3399.
> Also add support for 10-bit 4:4:4 format while at it.
>=20
> V5: Use drm_format_info_min_pitch() for correct bpp
> =C2=A0=C2=A0=C2=A0 Add missing NV21, NV61 and NV42 formats
> V4: Rework RK3328/RK3399 win0/1 data to not affect RK3368
> V2: Added NV30 support
>=20
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Reviewed-by: Sandy Huang <hjc@rock-chips.com>

Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Tested-by: Christopher Obbard <chris.obbard@collabora.com>


Cheers!

Chris

> ---
> =C2=A0drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 ++++++++---
> =C2=A0drivers/gpu/drm/rockchip/rockchip_drm_vop.h |=C2=A0 1 +
> =C2=A0drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 66 +++++++++++++++++-=
---
> =C2=A03 files changed, 86 insertions(+), 17 deletions(-)
>=20
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> index 14320bc73e5b..b3d0b6ae9294 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> @@ -272,6 +272,18 @@ static bool has_uv_swapped(uint32_t format)
> =C2=A0	}
> =C2=A0}
> =C2=A0
> +static bool is_fmt_10(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_NV15:
> +	case DRM_FORMAT_NV20:
> +	case DRM_FORMAT_NV30:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> =C2=A0static enum vop_data_format vop_convert_format(uint32_t format)
> =C2=A0{
> =C2=A0	switch (format) {
> @@ -287,12 +299,15 @@ static enum vop_data_format
> vop_convert_format(uint32_t format)
> =C2=A0	case DRM_FORMAT_BGR565:
> =C2=A0		return VOP_FMT_RGB565;
> =C2=A0	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_NV15:
> =C2=A0	case DRM_FORMAT_NV21:
> =C2=A0		return VOP_FMT_YUV420SP;
> =C2=A0	case DRM_FORMAT_NV16:
> +	case DRM_FORMAT_NV20:
> =C2=A0	case DRM_FORMAT_NV61:
> =C2=A0		return VOP_FMT_YUV422SP;
> =C2=A0	case DRM_FORMAT_NV24:
> +	case DRM_FORMAT_NV30:
> =C2=A0	case DRM_FORMAT_NV42:
> =C2=A0		return VOP_FMT_YUV444SP;
> =C2=A0	default:
> @@ -944,7 +959,12 @@ static void vop_plane_atomic_update(struct drm_plane
> *plane,
> =C2=A0	dsp_sty =3D dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
> =C2=A0	dsp_st =3D dsp_sty << 16 | (dsp_stx & 0xffff);
> =C2=A0
> -	offset =3D (src->x1 >> 16) * fb->format->cpp[0];
> +	if (fb->format->char_per_block[0])
> +		offset =3D drm_format_info_min_pitch(fb->format, 0,
> +						=C2=A0=C2=A0 src->x1 >> 16);
> +	else
> +		offset =3D (src->x1 >> 16) * fb->format->cpp[0];
> +
> =C2=A0	offset +=3D (src->y1 >> 16) * fb->pitches[0];
> =C2=A0	dma_addr =3D rk_obj->dma_addr + offset + fb->offsets[0];
> =C2=A0
> @@ -970,6 +990,7 @@ static void vop_plane_atomic_update(struct drm_plane
> *plane,
> =C2=A0	}
> =C2=A0
> =C2=A0	VOP_WIN_SET(vop, win, format, format);
> +	VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
> =C2=A0	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
> =C2=A0	VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
> =C2=A0	VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
> @@ -979,15 +1000,16 @@ static void vop_plane_atomic_update(struct drm_pla=
ne
> *plane,
> =C2=A0		=C2=A0=C2=A0=C2=A0 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1=
 : 0);
> =C2=A0
> =C2=A0	if (is_yuv) {
> -		int hsub =3D fb->format->hsub;
> -		int vsub =3D fb->format->vsub;
> -		int bpp =3D fb->format->cpp[1];
> -
> =C2=A0		uv_obj =3D fb->obj[1];
> =C2=A0		rk_uv_obj =3D to_rockchip_obj(uv_obj);
> =C2=A0
> -		offset =3D (src->x1 >> 16) * bpp / hsub;
> -		offset +=3D (src->y1 >> 16) * fb->pitches[1] / vsub;
> +		if (fb->format->char_per_block[1])
> +			offset =3D drm_format_info_min_pitch(fb->format, 1,
> +							=C2=A0=C2=A0 src->x1 >> 16);
> +		else
> +			offset =3D (src->x1 >> 16) * fb->format->cpp[1];
> +		offset /=3D fb->format->hsub;
> +		offset +=3D (src->y1 >> 16) * fb->pitches[1] / fb->format-
> >vsub;
> =C2=A0
> =C2=A0		dma_addr =3D rk_uv_obj->dma_addr + offset + fb->offsets[1];
> =C2=A0		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1],
> 4));
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> index 5f56e0597df8..4b2daefeb8c1 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> @@ -186,6 +186,7 @@ struct vop_win_phy {
> =C2=A0	struct vop_reg enable;
> =C2=A0	struct vop_reg gate;
> =C2=A0	struct vop_reg format;
> +	struct vop_reg fmt_10;
> =C2=A0	struct vop_reg rb_swap;
> =C2=A0	struct vop_reg uv_swap;
> =C2=A0	struct vop_reg act_info;
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> index 7b2805006776..f8cef0cb7bff 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
> @@ -53,6 +53,26 @@ static const uint32_t formats_win_full[] =3D {
> =C2=A0	DRM_FORMAT_NV42,
> =C2=A0};
> =C2=A0
> +static const uint32_t formats_win_full_10[] =3D {
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_RGB888,
> +	DRM_FORMAT_BGR888,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_BGR565,
> +	DRM_FORMAT_NV12,
> +	DRM_FORMAT_NV21,
> +	DRM_FORMAT_NV16,
> +	DRM_FORMAT_NV61,
> +	DRM_FORMAT_NV24,
> +	DRM_FORMAT_NV42,
> +	DRM_FORMAT_NV15,
> +	DRM_FORMAT_NV20,
> +	DRM_FORMAT_NV30,
> +};
> +
> =C2=A0static const uint64_t format_modifiers_win_full[] =3D {
> =C2=A0	DRM_FORMAT_MOD_LINEAR,
> =C2=A0	DRM_FORMAT_MOD_INVALID,
> @@ -627,11 +647,12 @@ static const struct vop_scl_regs rk3288_win_full_sc=
l =3D
> {
> =C2=A0
> =C2=A0static const struct vop_win_phy rk3288_win01_data =3D {
> =C2=A0	.scl =3D &rk3288_win_full_scl,
> -	.data_formats =3D formats_win_full,
> -	.nformats =3D ARRAY_SIZE(formats_win_full),
> +	.data_formats =3D formats_win_full_10,
> +	.nformats =3D ARRAY_SIZE(formats_win_full_10),
> =C2=A0	.format_modifiers =3D format_modifiers_win_full,
> =C2=A0	.enable =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
> =C2=A0	.format =3D VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
> +	.fmt_10 =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
> =C2=A0	.rb_swap =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
> =C2=A0	.uv_swap =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
> =C2=A0	.act_info =3D VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
> @@ -936,13 +957,38 @@ static const struct vop_win_yuv2yuv_data
> rk3399_vop_big_win_yuv2yuv_data[] =3D {
> =C2=A0
> =C2=A0};
> =C2=A0
> -static const struct vop_win_phy rk3399_win01_data =3D {
> +static const struct vop_win_phy rk3399_win0_data =3D {
> =C2=A0	.scl =3D &rk3288_win_full_scl,
> -	.data_formats =3D formats_win_full,
> -	.nformats =3D ARRAY_SIZE(formats_win_full),
> +	.data_formats =3D formats_win_full_10,
> +	.nformats =3D ARRAY_SIZE(formats_win_full_10),
> =C2=A0	.format_modifiers =3D format_modifiers_win_full_afbc,
> =C2=A0	.enable =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
> =C2=A0	.format =3D VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
> +	.fmt_10 =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
> +	.rb_swap =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
> +	.uv_swap =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
> +	.x_mir_en =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
> +	.y_mir_en =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
> +	.act_info =3D VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
> +	.dsp_info =3D VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
> +	.dsp_st =3D VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
> +	.yrgb_mst =3D VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
> +	.uv_mst =3D VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
> +	.yrgb_vir =3D VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
> +	.uv_vir =3D VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
> +	.src_alpha_ctl =3D VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
> +	.dst_alpha_ctl =3D VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
> +	.channel =3D VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
> +};
> +
> +static const struct vop_win_phy rk3399_win1_data =3D {
> +	.scl =3D &rk3288_win_full_scl,
> +	.data_formats =3D formats_win_full_10,
> +	.nformats =3D ARRAY_SIZE(formats_win_full_10),
> +	.format_modifiers =3D format_modifiers_win_full,
> +	.enable =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
> +	.format =3D VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
> +	.fmt_10 =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
> =C2=A0	.rb_swap =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
> =C2=A0	.uv_swap =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
> =C2=A0	.x_mir_en =3D VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
> @@ -965,9 +1011,9 @@ static const struct vop_win_phy rk3399_win01_data =
=3D {
> =C2=A0 * AFBC on the primary plane.
> =C2=A0 */
> =C2=A0static const struct vop_win_data rk3399_vop_win_data[] =3D {
> -	{ .base =3D 0x00, .phy =3D &rk3399_win01_data,
> +	{ .base =3D 0x00, .phy =3D &rk3399_win0_data,
> =C2=A0	=C2=A0 .type =3D DRM_PLANE_TYPE_PRIMARY },
> -	{ .base =3D 0x40, .phy =3D &rk3368_win01_data,
> +	{ .base =3D 0x40, .phy =3D &rk3399_win1_data,
> =C2=A0	=C2=A0 .type =3D DRM_PLANE_TYPE_OVERLAY },
> =C2=A0	{ .base =3D 0x00, .phy =3D &rk3368_win23_data,
> =C2=A0	=C2=A0 .type =3D DRM_PLANE_TYPE_OVERLAY },
> @@ -1099,11 +1145,11 @@ static const struct vop_intr rk3328_vop_intr =3D =
{
> =C2=A0};
> =C2=A0
> =C2=A0static const struct vop_win_data rk3328_vop_win_data[] =3D {
> -	{ .base =3D 0xd0, .phy =3D &rk3368_win01_data,
> +	{ .base =3D 0xd0, .phy =3D &rk3399_win1_data,
> =C2=A0	=C2=A0 .type =3D DRM_PLANE_TYPE_PRIMARY },
> -	{ .base =3D 0x1d0, .phy =3D &rk3368_win01_data,
> +	{ .base =3D 0x1d0, .phy =3D &rk3399_win1_data,
> =C2=A0	=C2=A0 .type =3D DRM_PLANE_TYPE_OVERLAY },
> -	{ .base =3D 0x2d0, .phy =3D &rk3368_win01_data,
> +	{ .base =3D 0x2d0, .phy =3D &rk3399_win1_data,
> =C2=A0	=C2=A0 .type =3D DRM_PLANE_TYPE_CURSOR },
> =C2=A0};
> =C2=A0