Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31;
Date:   Tue, 24 Oct 2023 00:43:05 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
Cc:     davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
        pabeni@redhat.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        corbet@lwn.net, steen.hegelund@microchip.com,
        rdunlap@infradead.org, horms@kernel.org, casper.casan@gmail.com,
        netdev@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
        horatiu.vultur@microchip.com, Woojung.Huh@microchip.com,
        Nicolas.Ferre@microchip.com, UNGLinuxDriver@microchip.com,
        Thorsten.Kummermehr@microchip.com
Subject: Re: [PATCH net-next v2 2/9] net: ethernet: oa_tc6: implement mac-phy
 software reset
Message-ID: <219ae3d7-0c75-49c0-b791-5623894ba318@lunn.ch>
References: <20231023154649.45931-1-Parthiban.Veerasooran@microchip.com>
 <20231023154649.45931-3-Parthiban.Veerasooran@microchip.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20231023154649.45931-3-Parthiban.Veerasooran@microchip.com>
Precedence: bulk

> +	ret = oa_tc6_perform_ctrl(tc6, RESET, &regval, 1, true, true);
> +	ret = oa_tc6_perform_ctrl(tc6, RESET, &regval, 1, true, false);

Just looking at this, it is not clear what these true/false mean. Maybe add some #defines

#define TC6_READ true
#define TC6_WRITE false
#define TC6_PROTECTED true
#define TC6_UNPROTECTED false

> +	if (ret)
> +		return ret;
> +
> +	/* The chip completes a reset in 3us, we might get here earlier than
> +	 * that, as an added margin we'll conditionally sleep 5us.
> +	 */
> +	udelay(5);
> +
> +	ret = oa_tc6_perform_ctrl(tc6, STATUS0, &regval, 1, false, false);
> +	if (ret)
> +		return ret;
> +
> +	/* Check for reset complete interrupt status */
> +	if (regval & RESETC) {
> +		regval = RESETC;

People don't always agree, but i found STATUS0_RESETC easier to see
you have the correct bit for the register you just read.

	Andrew