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Message-ID: <a55df8fa-122f-4721-94ac-5a2ca4cc7e26@gmail.com>
Date:   Mon, 23 Oct 2023 18:49:40 -0700
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Subject: Re: [PATCH 01/11] MIPS: compressed: Use correct instruction for 64
 bit code
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To:     Gregory CLEMENT <gregory.clement@bootlin.com>,
        Paul Burton <paulburton@kernel.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-mips@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     Vladimir Kondratiev <vladimir.kondratiev@intel.com>,
        Tawfik Bayouk <tawfik.bayouk@mobileye.com>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        =?UTF-8?Q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>
References: <20231004161038.2818327-1-gregory.clement@bootlin.com>
 <20231004161038.2818327-2-gregory.clement@bootlin.com>
From:   Florian Fainelli <f.fainelli@gmail.com>
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In-Reply-To: <20231004161038.2818327-2-gregory.clement@bootlin.com>
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On 10/4/2023 9:10 AM, Gregory CLEMENT wrote:
> The code clearing BSS already use macro or use correct instruction
> depending id the CPU is 32 bits or 64 bits.

s/id/if/

> However, a few
> instructions remained 32 bits only.
> 
> By using the accurate MACRO, it is now possible to deal with memory
> address beyond 32 bits. As a side effect, when using 64bits processor,
> it also divides the loop number needed to clear the BSS by 2.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>

> ---
>   arch/mips/boot/compressed/head.S | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
> index 5795d0af1e1b..d237a834b85e 100644
> --- a/arch/mips/boot/compressed/head.S
> +++ b/arch/mips/boot/compressed/head.S
> @@ -25,8 +25,8 @@
>   	/* Clear BSS */
>   	PTR_LA	a0, _edata
>   	PTR_LA	a2, _end
> -1:	sw	zero, 0(a0)
> -	addiu	a0, a0, 4
> +1:	PTR_S	zero, 0(a0)
> +	PTR_ADDIU a0, a0, PTRSIZE
>   	bne	a2, a0, 1b
>   
>   	PTR_LA	a0, (.heap)	     /* heap address */

-- 
Florian