Content-class: urn:content-classes:message
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Subject: RE: [patch][v2] x86, ptrace: support for branch trace store(BTS)
Date: Tue, 20 Nov 2007 15:49:03 -0000
Message-ID: <029E5BE7F699594398CA44E3DDF55444F71289@swsmsx413.ger.corp.intel.com>
In-Reply-To: <alpine.DEB.0.99999.0711200729570.765@twinlark.arctic.org>
Thread-Topic: [patch][v2] x86, ptrace: support for branch trace store(BTS)
thread-index: Acgri0zyGvL16xsdTTahFnbyR3HzWAAAFeEQ
References: <029E5BE7F699594398CA44E3DDF55444F3AEA7@swsmsx413.ger.corp.intel.com> <alpine.DEB.0.99999.0711200708580.765@twinlark.arctic.org> <alpine.DEB.0.99999.0711200729570.765@twinlark.arctic.org>
From: "Metzger, Markus T" <markus.t.metzger@intel.com>
To: "dean gaudet" <dean@arctic.org>
Cc: <linux-kernel@vger.kernel.org>, <mingo@elte.hu>, <hpa@zytor.com>,
       <tglx@linutronix.de>, <ak@suse.de>,
       "Siddha, Suresh B" <suresh.b.siddha@intel.com>,
       <akpm@linux-foundation.org>
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>-----Original Message-----
>From: dean gaudet [mailto:dean@arctic.org] 
>Sent: Dienstag, 20. November 2007 16:37
>To: Metzger, Markus T
>Cc: linux-kernel@vger.kernel.org; mingo@elte.hu; 
>hpa@zytor.com; tglx@linutronix.de; ak@suse.de; Siddha, Suresh 
>B; akpm@linux-foundation.org
>Subject: Re: [patch][v2] x86, ptrace: support for branch trace 
>store(BTS)
>
>On Tue, 20 Nov 2007, dean gaudet wrote:
>
>> On Tue, 20 Nov 2007, Metzger, Markus T wrote:
>> 
>> > +__cpuinit void ptrace_bts_init_intel(struct cpuinfo_x86 *c)
>> > +{
>> > +	switch (c->x86) {
>> > +	case 0x6:
>> > +		switch (c->x86_model) {
>> > +#ifdef __i386__
>> > +		case 0xD:
>> > +		case 0xE: /* Pentium M */
>> > +			ptrace_bts_ops = ptrace_bts_ops_pentium_m;
>> > +			break;
>> > +#endif /* _i386_ */
>> > +		case 0xF: /* Core2 */
>> > +			ptrace_bts_ops = ptrace_bts_ops_core2;
>> > +			break;
>> > +		default:
>> > +			/* sorry, don't know about them */
>> > +			break;
>> > +		}
>> > +		break;
>> > +	case 0xF:
>> > +		switch (c->x86_model) {
>> > +#ifdef __i386__
>> > +		case 0x0:
>> > +		case 0x1:
>> > +		case 0x2:
>> > +		case 0x3: /* Netburst */
>> > +			ptrace_bts_ops = ptrace_bts_ops_netburst;
>> > +			break;
>> > +#endif /* _i386_ */
>> > +		default:
>> > +			/* sorry, don't know about them */
>> > +			break;
>> > +		}
>> > +		break;
>> 
>> is this right?  i thought intel family 15 models 3 and 4 
>supported amd64
>> mode...
>
>actually... why aren't you using cpuid level 1 edx bit 21 to 
>enable/disable this feature?  isn't that the bit defined to indicate 
>whether this feature is supported or not?

This function is not checking for the presence of the feature 
but for the BTS record format.
The feature check is done in init_intel().


>and it seems like this patch and perfmon2 are going to have to 
>live with 
>each other... since they both require the use of the DS save area...

Hmmm, this might require some synchronization between those two.

Do you know how (accesses to) MSR's are managed by the kernel?

regards,
markus.

>
>-dean
>
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