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Tue, 24 Oct 2023 07:03:45 -0700 (PDT) >> > After looking at Yishai's virtio-vfio-pci driver where BAR0 is emulate= d=0A= >> > as an IO Port BAR, it occurs to me that there's no config space=0A= >> > emulation of BAR2 (or BAR3) here.=A0 Doesn't this mean that QEMU regis= ters=0A= >> > the BAR as 32-bit, non-prefetchable?=A0 ie. VFIOBAR.type & .mem64 are= =0A= >> > wrong?=0A= >>=0A= >> Maybe I didn't understand the question, but the PCI config space read/wr= ite=0A= >> would still be handled by vfio_pci_core_read/write() which returns the= =0A= >> appropriate flags. I have checked that the device BARs are 64b and=0A= >> prefetchable in the VM.=0A= >=0A= > vfio_pci_core_read/write() accesses the physical device, which doesn't=0A= > implement BAR2.=A0 Why would an unimplemented BAR2 on the physical device= =0A= > report 64-bit, prefetchable?=0A= >=0A= > QEMU records VFIOBAR.type and .mem64 from reading the BAR register in=0A= > vfio_bar_prepare() and passes this type to pci_register_bar() in=0A= > vfio_bar_register().=A0 Without an implementation of a config space read= =0A= > op in the variant driver and with no physical implementation of BAR2 on= =0A= > the device, I don't see how we get correct values in these fields.=0A= =0A= I think I see the cause of confusion. There are real PCIe compliant BARs=0A= present on the device, just that it isn't being used once the C2C=0A= interconnect is active. The BARs are 64b prefetchable. Here it the lspci=0A= snippet of the device on the host.=0A= # lspci -v -s 9:1:0.0=0A= 0009:01:00.0 3D controller: NVIDIA Corporation Device 2342 (rev a1)=0A= Subsystem: NVIDIA Corporation Device 16eb=0A= Physical Slot: 0-5=0A= Flags: bus master, fast devsel, latency 0, IRQ 263, NUMA node 0, IO= MMU group 19=0A= Memory at 661002000000 (64-bit, prefetchable) [size=3D16M]=0A= Memory at 662000000000 (64-bit, prefetchable) [size=3D128G]=0A= Memory at 661000000000 (64-bit, prefetchable) [size=3D32M]=0A= =0A= I suppose this answers the BAR sizing question as well?=