Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2;
MIME-Version: 1.0
References: <1696440338-12561-1-git-send-email-quic_mojha@quicinc.com> <1696440338-12561-4-git-send-email-quic_mojha@quicinc.com>
In-Reply-To: <1696440338-12561-4-git-send-email-quic_mojha@quicinc.com>
From:   Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date:   Tue, 24 Oct 2023 22:53:56 +0300
Message-ID: <CAA8EJpoWfiwr2ADWuej8+RkNqmP-=tbNq=me_ok72iuG6m9sug@mail.gmail.com>
Subject: Re: [PATCH v7 3/3] firmware: scm: Modify only the download bits in
 TCSR register
To:     Mukesh Ojha <quic_mojha@quicinc.com>
Cc:     agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org,
        p.zabel@pengutronix.de, linus.walleij@linaro.org,
        linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Wed, 4 Oct 2023 at 20:28, Mukesh Ojha <quic_mojha@quicinc.com> wrote:
>
> Crashdump collection is based on the DLOAD bit of TCSR register.
> To retain other bits, we read the register and modify only the
> DLOAD bit as the other bits have their own significance.

Nit: please take a look at
`Documentation/process/submitting-patches.rst`: `Describe your changes
in imperative mood'.

We do not read registers. Driver does. Nevertheless, this is a minor
issue, which shouldn't prevent this patch from being applied.

>
> Co-developed-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
> Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
> Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
> Tested-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> # IPQ9574 and IPQ5332

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> ---
>  drivers/firmware/qcom_scm.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> index 084e4782b88d..da3d028f6451 100644
> --- a/drivers/firmware/qcom_scm.c
> +++ b/drivers/firmware/qcom_scm.c
> @@ -4,6 +4,8 @@
>   */
>
>  #include <linux/arm-smccc.h>
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
>  #include <linux/clk.h>
>  #include <linux/completion.h>
>  #include <linux/cpumask.h>
> @@ -27,6 +29,10 @@
>  static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
>  module_param(download_mode, bool, 0);
>
> +#define QCOM_DLOAD_MASK                GENMASK(5, 4)
> +#define QCOM_DLOAD_FULLDUMP    0x1
> +#define QCOM_DLOAD_NODUMP      0x0

Nit: it might be better to move these defines after all struct definitions.

> +
>  struct qcom_scm {
>         struct device *dev;
>         struct clk *core_clk;
> @@ -518,6 +524,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
>
>  static void qcom_scm_set_download_mode(bool enable)
>  {
> +       u32 val = enable ? QCOM_DLOAD_FULLDUMP : QCOM_DLOAD_NODUMP;
>         bool avail;
>         int ret = 0;
>
> @@ -527,8 +534,9 @@ static void qcom_scm_set_download_mode(bool enable)
>         if (avail) {
>                 ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
>         } else if (__scm->dload_mode_addr) {
> -               ret = qcom_scm_io_writel(__scm->dload_mode_addr,
> -                               enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
> +               ret = qcom_scm_io_update_field(__scm->dload_mode_addr,
> +                                              QCOM_DLOAD_MASK,
> +                                              FIELD_PREP(QCOM_DLOAD_MASK, val));
>         } else {
>                 dev_err(__scm->dev,
>                         "No available mechanism for setting download mode\n");
> --
> 2.7.4
>


-- 
With best wishes
Dmitry