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Date:   Wed, 25 Oct 2023 15:12:20 +0100
From:   Conor Dooley <conor@kernel.org>
To:     shravan chippa <shravan.chippa@microchip.com>
Cc:     green.wan@sifive.com, vkoul@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com,
        paul.walmsley@sifive.com, conor+dt@kernel.org,
        dmaengine@vger.kernel.org, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        nagasuresh.relli@microchip.com, praveen.kumar@microchip.com
Subject: Re: [PATCH v3 4/4] riscv: dts: microchip: add specific compatible
 for mpfs' pdma
Message-ID: <20231025-pang-unstuffed-4d8bf48baf21@spud>
References: <20231025102251.3369472-1-shravan.chippa@microchip.com>
 <20231025102251.3369472-5-shravan.chippa@microchip.com>
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On Wed, Oct 25, 2023 at 03:52:51PM +0530, shravan chippa wrote:
> From: Shravan Chippa <shravan.chippa@microchip.com>
>=20
> Add specific compatible for PolarFire SoC for The SiFive PDMA driver
>=20

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com>
> ---
>  arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dt=
s/microchip/mpfs.dtsi
> index 104504352e99..f43486e9a090 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -221,7 +221,7 @@ plic: interrupt-controller@c000000 {
>  		};
> =20
>  		pdma: dma-controller@3000000 {
> -			compatible =3D "sifive,fu540-c000-pdma", "sifive,pdma0";
> +			compatible =3D "microchip,mpfs-pdma", "sifive,pdma0";
>  			reg =3D <0x0 0x3000000 0x0 0x8000>;
>  			interrupt-parent =3D <&plic>;
>  			interrupts =3D <5 6>, <7 8>, <9 10>, <11 12>;
> --=20
> 2.34.1
>=20

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