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From:   Ankit Agrawal <ankita@nvidia.com>
To:     Alex Williamson <alex.williamson@redhat.com>
CC:     "Tian, Kevin" <kevin.tian@intel.com>,
        Jason Gunthorpe <jgg@nvidia.com>,
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        <shameerali.kolothum.thodi@huawei.com>,
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        "Anuj Aggarwal (SW-GPU)" <anuaggarwal@nvidia.com>,
        "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v12 1/1] vfio/nvgpu: Add vfio pci variant module for grace
 hopper
Thread-Topic: [PATCH v12 1/1] vfio/nvgpu: Add vfio pci variant module for
 grace hopper
Thread-Index: AQHZ/4T6dPreO49caEWsaHN/ceuQqrBOmsSAgAi/5YSAACTLAIABhTmtgAAJHQCAAS20AIAAOkSMgAAn94CAACslEw==
Date:   Wed, 25 Oct 2023 17:15:12 +0000
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References: <20231015163047.20391-1-ankita@nvidia.com>
        <20231017165437.69a84f0c.alex.williamson@redhat.com>
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        <20231023084312.15b8e37e.alex.williamson@redhat.com>
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        <20231024082854.0b767d74.alex.williamson@redhat.com>
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 <20231025082019.14575863.alex.williamson@redhat.com>
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> BTW, it's still never been answered why the latest QEMU series dropped=0A=
> the _DSD support.=0A=
=0A=
The _DSD keys were there in v1 to communicate the PXM start id and the=0A=
count associated with the device to the VM kernel. In v2, we proposed an=0A=
alternative approach to leverage the Generic Initiator (GI) Affinity struct=
ure=0A=
in SRAT (ACPI Spec 6.5, Section 5.2.16.6) to create NUMA nodes. GI structur=
e=0A=
allows an association between a GI (GPU in this case) and proximity domains=
.=0A=
So we create 8 GI structures with a unique PXM Id and the device BDF. This=
=0A=
removes the need for DSD keys as the VM kernel could parse the GI structure=
s=0A=
and identify the PXM IDs associated with the device using the BDF.=0A=
(E.g. https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/amd/am=
dkfd/kfd_crat.c#L1938)=0A=
=0A=
> In light of that, I don't think we should be independently calculating=0A=
> the BAR2 region size using roundup_pow_of_two(nvdev->memlength).=0A=
> Instead we should be using pci_resource_len() of the physical BAR2 to=0A=
> make it evident that this relationship exists.=0A=
=0A=
Sure, I will make the change in the next posting.=0A=
=0A=
> The comments throughout should also be updated to reflect this as=0A=
> currently they're written as if there is no physical BAR2 and we're=0A=
> making a completely independent decision relative to BAR2 sizing.=A0 A=0A=
> comment should also be added to nvgrace_gpu_vfio_pci_read/write()=0A=
> explaining that the physical BAR2 provides the correct behavior=0A=
> relative to config space accesses.=0A=
=0A=
Yeah, will update the comments.=0A=
=0A=
> The probe function should also fail if pci_resource_len() for BAR2 is=0A=
> not sufficient for the coherent memory region.=A0 Thanks,=0A=
=0A=
Ack.=0A=
=0A=