Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32;
MIME-Version: 1.0
From:   Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date:   Wed, 25 Oct 2023 11:56:35 -0700
Message-ID: <CAJM55Z_pdoGxRXbmBgJ5GbVWyeM1N6+LHihbNdT26Oo_qA5VYA@mail.gmail.com>
Subject: [PATCH 0/4] soc: sifive: ccache: Add StarFive JH7100 support
To:     linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

This series adds support for the StarFive JH7100 SoC to the SiFive cache
controller driver. The JH7100 was a "development version" of the JH7110
used on the BeagleV Starlight and VisionFive V1 boards.  It has
non-coherent peripheral DMAs but was designed before the standard RISC-V
Zicbom extension, so it neeeds support in this driver for non-standard
cache management.

Emil Renner Berthing (4):
  dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
  soc: sifive: ccache: Add StarFive JH7100 support
  dt-bindings: cache: sifive,ccache0: Add sifive,cache-ops property
  soc: sifive: ccache: Support cache management operations

 .../bindings/cache/sifive,ccache0.yaml        | 11 +++-
 drivers/soc/sifive/sifive_ccache.c            | 56 ++++++++++++++++++-
 2 files changed, 64 insertions(+), 3 deletions(-)

-- 
2.40.1