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From:   Emil Renner Berthing <emil.renner.berthing@canonical.com>
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References: <CAJM55Z_pdoGxRXbmBgJ5GbVWyeM1N6+LHihbNdT26Oo_qA5VYA@mail.gmail.com>
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Date:   Wed, 25 Oct 2023 12:06:50 -0700
Message-ID: <CAJM55Z9gy4RFXqu8n5jtW4k2gwDtpJDkevdLht9rMyL=464AMg@mail.gmail.com>
Subject: Re: [PATCH 0/4] soc: sifive: ccache: Add StarFive JH7100 support
To:     Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>
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Emil Renner Berthing wrote:
> This series adds support for the StarFive JH7100 SoC to the SiFive cache
> controller driver. The JH7100 was a "development version" of the JH7110
> used on the BeagleV Starlight and VisionFive V1 boards.  It has
> non-coherent peripheral DMAs but was designed before the standard RISC-V
> Zicbom extension, so it neeeds support in this driver for non-standard
> cache management.

Ugh, sorry about the broken threading and From vs. Signed-off-by's.
Will fix in v2.

/Emil