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Wed, 25 Oct 2023 14:11:48 -0700 (PDT) Date: Wed, 25 Oct 2023 14:11:45 -0700 From: Charlie Jenkins To: Arnd Bergmann Cc: "Wang, Xiao W" , Linux-Arch , Albert Ou , "linux-kernel@vger.kernel.org" , Conor Dooley , David Laight , Palmer Dabbelt , Paul Walmsley , "linux-riscv@lists.infradead.org" Subject: Re: [PATCH v7 2/4] riscv: Checksum header Message-ID: References: <20230919-optimize_checksum-v7-0-06c7d0ddd5d6@rivosinc.com> <20230919-optimize_checksum-v7-2-06c7d0ddd5d6@rivosinc.com> <059f17e6-e240-40fa-8742-7844ad3b3502@app.fastmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <059f17e6-e240-40fa-8742-7844ad3b3502@app.fastmail.com> X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 25 Oct 2023 14:12:01 -0700 (PDT) On Wed, Oct 25, 2023 at 10:52:22PM +0200, Arnd Bergmann wrote: > On Wed, Oct 25, 2023, at 22:37, Charlie Jenkins wrote: > > On Wed, Oct 25, 2023 at 06:50:05AM +0000, Wang, Xiao W wrote: > > >> > + > >> > +/* > >> > + * Quickly compute an IP checksum with the assumption that IPv4 headers > >> > will > >> > + * always be in multiples of 32-bits, and have an ihl of at least 5. > >> > + * @ihl is the number of 32 bit segments and must be greater than or equal > >> > to 5. > >> > + * @iph is assumed to be word aligned. > >> > >> Not sure if the assumption is always true. It looks the implementation in "lib/checksum.c" doesn't take this assumption. > >> The ip header can comes after a 14-Byte ether header, which may start from a word-aligned or DMA friendly address. > > > > While lib/checksum.c does not make this assumption, other architectures > > (x86, ARM, powerpc, mips, arc) do make this assumption. Architectures > > seem to only align the header on a word boundary in do_csum. I worry > > that the benefit of aligning iph in this "fast" csum function would > > disproportionately impact hardware that has fast misaligned accesses. > > Most architectures set NET_IP_ALIGN to '2', which is intended > to have the IP header at a 32-bit aligned address, though > some other targets don't bother: > > arch/arm64/include/asm/processor.h:#define NET_IP_ALIGN 0 > arch/powerpc/include/asm/processor.h:#define NET_IP_ALIGN 0 > arch/x86/include/asm/processor.h:#define NET_IP_ALIGN 0 > include/linux/skbuff.h:#define NET_IP_ALIGN 2 > > I think it's considered a driver bug if an SKB ends up > with a misaligned IP header, but it's also something that > some of the more obscure drivers get wrong. > > Arnd Thank you for pointing that out, I had not realized that macro existed. Since riscv keeps NET_IP_ALIGN at 0 it should be expected that ip_fast_csum is only called with 32-bit aligned addresses. I will update the comment and refer to that macro. riscv supports misaligned accesses but there are no guarantees of speed. - Charlie