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Wed, 25 Oct 2023 22:34:12 -0700 (PDT) On 10/25/2023 1:22 PM, Manivannan Sadhasivam wrote: > On Thu, Oct 19, 2023 at 05:07:10PM +0530, Mrinmay Sarkar wrote: >> Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. >> It supports gen4 and x2 link width. Due to some stability issue in >> gen4 enabling gen3 as of now. >> >> Signed-off-by: Mrinmay Sarkar >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 48 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 48 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 13dd44d..2aa7383 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -3714,4 +3714,52 @@ >> >> status = "disabled"; >> }; >> + >> + pcie0_ep: pcie-ep@1c00000 { >> + compatible = "qcom,sa8775p-pcie-ep"; >> + reg = <0x0 0x01c00000 0x0 0x3000>, >> + <0x0 0x40000000 0x0 0xf20>, >> + <0x0 0x40000f20 0x0 0xa8>, >> + <0x0 0x40001000 0x0 0x4000>, >> + <0x0 0x40200000 0x0 0x100000>, >> + <0x0 0x01c03000 0x0 0x1000>, >> + <0x0 0x40005000 0x0 0x2000>; > Can we sort the reg entries? > >> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", >> + "mmio", "dma"; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; >> + >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a"; >> + >> + interrupts = , >> + , >> + ; >> + >> + interrupt-names = "global", "doorbell", "dma"; >> + >> + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; >> + interconnect-names = "pcie-mem", "cpu-pcie"; >> + >> + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, >> + <0x100 &pcie_smmu 0x0001 0x1>; > I think I recommended using "iommu-map" instead of "iommus" property. But > looking at it again, I think it is fine to use just "iommus" property as the SID > will be associated with the EP directly. > > Unless you want to have different SID for each function. > >> + >> + resets = <&gcc GCC_PCIE_0_BCR>; >> + reset-names = "core"; >> + power-domains = <&gcc PCIE_0_GDSC>; >> + phys = <&pcie0_phy>; >> + phy-names = "pciephy"; >> + max-link-speed = <3>; > Please add a comment here that you are limiting the Gen speed due to stability > issues. Like, > > max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ > >> + num-lanes = <2>; > Can you check if the controller is cache coherent? If so, we should add > "dma-coherent" property. > > - Mani For cache coherency we need driver change as well. So will add this property along with driver change. --Mrinmay >> + >> + status = "disabled"; >> + }; >> }; >> -- >> 2.7.4 >>